EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 622

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–184
Figure 1–148. Rate Match FIFO Deletion with One Skip Pattern Deleted
Stratix IV Device Handbook Volume 2
rx_
rmfifodatadeleted
dataout
datain
Depending on your implementation, you can select two 20-bit rate match patterns in
the ALTGX MegaWizard Plug-In Manager under the What is the rate match pattern1
and What is the rate match pattern2 fields. Each of the two programmed 20-bit rate
match patterns consists of a 10-bit skip pattern and a 10-bit control pattern.
For Serial RapidIO mode in the ALTGX MegaWizard Plug-In Manager, the control
pattern1 defaults to K28.5 with positive disparity and the skip pattern1 defaults to
K29.7 with positive disparity. The control pattern2 defaults to K28.5 with negative
disparity and the skip pattern2 defaults to K29.7 with negative disparity.
The rate match FIFO operation begins after the word aligner synchronization status
rx_syncstatus goes high. When the rate matcher receives either of the two 10-bit
control patterns followed by the respective 10-bit skip pattern, it inserts or deletes the
10-bit skip pattern as necessary to avoid the rate match FIFO from overflowing or
under-running.
In Serial RapidIO mode, the rate match FIFO can delete/insert a maximum of one
skip pattern from a cluster.
Two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted, indicate that
rate match FIFO deletion and insertion events, respectively, are forwarded to the
FPGA fabric.
Figure 1–148
skip pattern is required to be deleted. In this example, the first skip cluster has a
/K28.5/ control pattern followed by two /K29.7/ skip patterns. The second skip
cluster has a /K28.5/ control pattern followed by four /K29.7/ skip patterns. The rate
match FIFO deletes only one /K29.7/ skip pattern from the first skip cluster. One
/K29.7/ skip pattern is deleted from the second cluster.
K28.5
K28.5
First Skip Cluster
K29.7
K29.7
shows an example of rate match FIFO deletion in the case where one
K29.7
K28.5
One Skip Pattern Deleted
K28.5
K29.7
Second Skip Cluster
K29.7
K29.7
K29.7
K29.7
Chapter 1: Stratix IV Transceiver Architecture
K29.7
K29.7
© March 2010 Altera Corporation
Transceiver Block Architecture
K29.7
Dx.y
Dx.y