EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 660
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX530HH35C2N PDF datasheet #7
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1–222
Table 1–77. Stratix IV GX and GT ALTGX Megafunction Ports: PCI Express (PIPE) Interface (Part 4 of 4)
Table 1–78. Stratix IV GX and GT ALTGX Megafunction Ports: Reset and Power Down (Part 1 of 2)
Stratix IV Device Handbook Volume 2
rx_pipedatavalid
pipeelecidle
gxb_powerdown
rx_digitalreset
Port Name
Port Name
Table 1–78
Output
Input/
Input
Input
Output
Output
Output
Input/
lists the ALTGX megafunction reset and power down ports.
refer the device
Characteristics
Clock Domain
Asynchronous
Asynchronous
requirements,
pulse width is
For minimum
clock cycles.
Clock Domain
Asynchronous
pulse width
two parallel
Switching
Minimum
chapter.
DC and
signal.
signal.
signal
N/A
Transceiver block power down.
■
■
Receiver PCS reset.
■
Valid data and control on the rx_dataout and
rx_ctrldetect ports indicator.
■
Electrical idle detected or inferred at the receiver
indicator.
■
■
■
When asserted high—all digital and analog
circuitry within the PCS, PMA, CMU channels, and
the CCU of the transceiver block, is powered down.
Asserting the gxb_powerdown signal does not
power down the REFCLK buffers.
When asserted high—the receiver PCS blocks are
reset. Refer to
Functionally equivalent to the rxvalid signal
defined in the PCI Express (PIPE) specification
revision 2.0.
Functionally equivalent to the rxelecidle
signal defined in the PCI Express (PIPE)
specification revision 2.0.
If the electrical idle inference block is enabled—
it drives this signal high when it infers an
electrical idle condition, as described in
“Electrical Idle Inference” on page
Otherwise, it drives this signal low.
If the electrical idle inference block is disabled—
the rx_signaldetect signal from the
signal detect circuitry in the receiver buffer is
inverted and driven on this port.
Reset Control and Power Down.
Description
Description
Chapter 1: Stratix IV Transceiver Architecture
© March 2010 Altera Corporation
1–136.
Transceiver Port Lists
Transceiver
Channel
Channel
Scope
Channel
Scope
block
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