EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 647

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Stratix IV Transceiver Architecture
Transceiver Port Lists
Table 1–73. Stratix IV GX and GT ALTGX Megafunction Ports: Transmitter Ports (Part 3 of 4)
© March 2010 Altera Corporation
tx_forcedisp
tx_dispval
tx_invpolarity
Port Name
Output
Input/
Input
Input
Input
pulse width is two
pulse width is two
pulse width is two
signal. Minimum
signal. Minimum
signal. Minimum
Asynchronous
Clock Domain
Asynchronous
Asynchronous
parallel clock
parallel clock
parallel clock
cycles.
cycles.
cycles.
8B/10B encoder force disparity control.
■
■
■
8B/10B encoder force disparity value.
■
■
■
Transmitter polarity inversion control. This
feature is useful for correcting situations in
which the positive and negative signals of the
differential serial link are accidentally swapped
during board layout.
■
■
When asserted high—forces the 8B/10B
encoder to encode the data on the
tx_datain port with a positive or
negative disparity depending on the
tx_dispval signal level.
When de-asserted low—the 8B/10B encoder
encodes the data on the tx_datain port
according to the 8B/10B running disparity
rules.
Channel Width:
8—tx_forcedisp = 1
16—tx_forcedisp = 2
32—tx_forcedisp = 4
A high level—when the tx_forcedisp
signal is asserted high, it forces the 8B/10B
encoder to encode the data on the
tx_datain port with a negative starting
running disparity.
A low level—when the tx_forcedisp
signal is asserted high, it forces the 8B/10B
encoder to encode the data on the
tx_datain port with a positive starting
running disparity.
Channel Width:
8—tx_dispval = 1
16—tx_dispval = 2
32—tx_dispval = 4
When asserted high in single-width
modes—the polarity of every bit of the 8-bit
or 10-bit input data to the serializer gets
inverted.
When asserted high in double-width
modes—the polarity of every bit of the
16-bit or 20-bit input data to the serializer
gets inverted.
Description
Stratix IV Device Handbook Volume 2
Channel
Channel
Channel
Scope
1–209