EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 621
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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Chapter 1: Stratix IV Transceiver Architecture
Transceiver Block Architecture
Figure 1–147. Synchronization State Machine in Serial RapidIO Mode
© March 2010 Altera Corporation
1
1
Figure 1–147
implemented in Serial RapidIO functional mode.
Rate Match FIFO in Serial RapidIO Mode
In Serial RapidIO mode, the rate match FIFO is capable of compensating for up to
±100 PPM (200 PPM total) difference between the upstream transmitter and the local
receiver reference clock.
To enable the rate match FIFO in Serial RapidIO mode, the transceiver channel must
have both the transmitter and receiver channel instantiated. You must select the
Receiver and Transmitter option in the What is the operation mode? field in the
ALTGX MegaWizard Plug-In Manager. The 8B/10B encoder/decoder is always
enabled in Serial RapidIO mode.
Rate matcher is an optional block available for selection in SRIO functional mode.
However, this block is not fully compliant to the SRIO specification.
Data = !Valid
ecntr = 3
shows a conceptual view of the synchronization state machine
Synchronized Error
if Data == Comma
if Data == !Valid
Comma Detect
Loss of Sync
Synchronized
if gcntr==255
kcntr=kcntr
kcntr++
ecntr++
gcntr=0
gcntr=0
gcntr++
Detect
ecntr--
else
else
else
Data = Comma
kcntr = 127
Data = !Valid
Data=Valid
ecntr = 0
Data = valid;
kcntr < 127
Stratix IV Device Handbook Volume 2
1–183
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