EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 553
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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Chapter 1: Stratix IV Transceiver Architecture
Transceiver Block Architecture
Figure 1–95. Transceiver Configurations in Basic Double-Width Mode with a 16-Bit PMA-PCS Interface for Stratix IV GT
Devices
Note to
(1) The maximum data rate specification shown in
© March 2010 Altera Corporation
other speed grades offered, refer to the
Figure
(FPGA Fabric-Transceiver
(1)
(FPGA Fabric-Transceiver
(1)
Interface Clock Cycles)
Interface Clock Cycles)
Interface Frequency
Interface Frequency
TX PCS Latency
Interface Frequency
RX PCS Latency
Data Rate (Gbps)
1–95:
Low-Latency PCS
Data Rate (Gbps)
Channel Bonding
Rate Match FIFO
Encoder/Decoder
Interface Width
(Pattern Length)
FPGA Fabric-
FPGA Fabric-
Interface Width
FPGA Fabric-
Byte Ordering
Transceiver
Transceiver
Word Aligner
Byte SerDes
Transceiver
PMA-PCS/Fabric
PMA-PCS
Interface Width
(MHz)
Functional
8B/10B
Modes
8-bit
Disabled
Disabled
2.488 –
Single
Width
16-bit
155 .5 -
11 - 13
4.0
250
5 - 6
Manual Alignment
10-bit
(8-, 16-, 32-bit)
DC and Switching Characteristics
Disabled
Disabled
Basic
Disabled
6.5 - 8.5
203.125
32-bit
77.75 –
16-bit
4 - 5.5
Figure 1–95
Enabled
2.488 –
Double
Width
6.5
Disabled
20-bit
6.5 - 8.5
Enabled
(Note 1)
203.125
77.75 –
32-bit
Stratix IV GT Configurations
4 - 5.5
is valid only for the -2 (fastest) speed grade devices. For data rate specifications for
Disabled
Disabled
2.488 –
155 .5 -
11 - 13
16-bit
250
5 - 6
4.0
(8-, 16-, 32-bit)
Disabled
Disabled
Bit-Slip
Basic Double Width
16-bit PMA-PCS
Interface Width
Disabled
Enabled
2.488 –
x1, x4, x8
1.0 – 8.5
203.125
32-bit
77.75 –
6.5 - 8.5
chapter.
4 - 5.5
6.5
PIPE
10-bit
XAUI
10-bit
Protocol
SRIO
10-bit
SONET
/SDH
8-bit
Disabled
Disabled
2.488 –
155.5 -
16-bit
3 - 4
4.0
250
4 - 5
Stratix IV Device Handbook Volume 2
16-bit
Disabled
Disabled
Disabled
Enabled
(OIF)
CEI
Disabled
Enabled
2.488 –
265.625
32-bit
77.75 –
10-bit
4 - 5.5
3 - 4.5
8.5
SDI
10-Bit
Deterministic
Latency
20-Bit
1–115
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