EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 853
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 5: Stratix IV Dynamic Reconfiguration
Dynamic Reconfiguration Modes Implementation
Figure 5–8. Method 2—Read Transaction Waveform
Note to
(1) To read the current V
© March 2010 Altera Corporation
Figure
5–8:
1
rx_tx_duplex_sel [1:0]
tx_vodctrl [5:0] (1)
OD
reconfig_clk
Figure 5–8
channels 1 and 2 prior to the read transaction are 3'b001 and 3'b010, respectively.
Simultaneous write and read transactions are not allowed.
Method 3—Using Individual Control Signals for Each Channel
You can optionally used Method 3 to individually reconfigure the PMA controls of
each transceiver channel.
When you disable the Use the same control signal for all channels option, the PMA
control ports for the write transaction are also separate for each channel. For example,
if you have two channels, tx_vodctrl is 6 bits wide (tx_vodctrl[2:0]
corresponds to channel 1 and tx_vodctrl[5:3] corresponds to channel 2).
The width of the PMA control ports for a read transaction are always separate for each
channel (the same as the PMA control ports, as explained in
Same Control Signals for All Channels” on page
values in channel 2, observe the values in tx_vodctrl_out[5:3].
data_valid
busy
read
shows the read transaction waveform. The transmit V
2’b00
6’b000000
2’b10 (transmitter portion only)
6’bXXXXXX
5–15.)
Stratix IV Device Handbook Volume 2
“Method 2—Using the
6’b010001
OD
settings written in
5–17
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