EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 635

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Stratix IV Transceiver Architecture
Auxiliary Transmit (ATX) PLL Block
Architecture of the ATX PLL Block
Figure 1–161. ATX PLL Block
Notes to
(1) In non-bonded functional modes (for example, CEI functional mode), the transmitter channel uses the transmitter local clock divider to divide this
(2) This is used in Basic ×4, ×8, and PCI Express (PIPE) ×4 and ×8 functional modes.
© March 2010 Altera Corporation
cascaded PLL clock
ITB clock lines
high-speed clock output to provide clocks for its PMA and PCS blocks.
global clock line
PCIErateswitch
pll_powerdown
Figure 1–161
f
8
1
:
For the 10G ATX PLL, Stratix IV GT devices only allow driving the reference clock
source from one of the dedicated reflck pins on the same side of the device.
For improved jitter performance, Altera strongly recommends using the REFCLK pins
of the transceiver block located immediately below the 10G ATX PLL block to drive
the input reference clock.
For more information about the input reference clocks for ATX PLLs, refer to the
Stratix IV Transceiver Clocking
Figure 1–161
and a shared control signal generation block).
The functional blocks on the ATX PLL are similar to the blocks explained in
PLL” on page
automatically selected by the Quartus II software based on the transceiver channel
configuration.
The ATX PLL high-speed clock output provides high-speed serial clocks for
non-bonded functional modes such as CEI (with the “none” subprotocol).
reference clock
ATX PLL input
shows the ATX PLL block components (the ATX PLL, ATX clock divider,
1–99. The values of the /M and /L divider settings in the ATX PLL are
ATX PLL
chapter.
PCI Express
rate switch
high-speed
controller
ATX PLL
Clock (1)
PCIE_gen2switch
PCIE_gen2switch_done
divider block
ATX clock
ATX PLL Block
Stratix IV Device Handbook Volume 2
high-speed serial clock
for bonded modes (2)
“CMU0
1–197