EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 666
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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2–2
Glossary of Terms
Table 2–1. Glossary of Terms Used in this chapter
Input Reference Clocking
Stratix IV Device Handbook Volume 2
ATX PLL
CDR
CMU
ITB lines
Convention
Table 2–1
Each transceiver block has:
■
■
Auxiliary transmit PLL block. For more information, refer to the “Auxiliary Transmit (ATX) PLL
Block” section in the
Clock data recovery block. For more information, refer to the “Clock and Data Recovery Unit”
section in the
Clock multiplier unit. For more information, refer to “CMU Channel Architecture” section in the
Stratix IV Transceiver Architecture
refclk pins of one transceiver block CMU PLLs and receiver CDRs of other transceiver blocks.
They also provide input reference clock to ATX PLLs. For more information, refer to
Transceiver Block (ITB) Clock Lines” on page
The Inter-Transceiver block (ITB) clock lines provide an input reference clock path from the
Two clock multiplier unit channels (CMU0_Channel and CMU1_Channel)
You can configure each as either a CMU to generate transceiver clocks or as a
PMA-Only channel.
f
Four regular channels
When the CMU channel is configured as a CMU, the CMU PLL synthesizes the
input reference clock to generate the high-speed serial transceiver clock. When the
CMU channel is configured as a Receiver Only or Receiver and Transmitter
channel, the CMU PLL acts as a CDR and uses the input reference clock as a
training clock when it is in lock-to-reference (LTR) mode. Each of the four regular
channels also has a receiver CDR that uses the input reference clock as a training
clock when it is in LTR mode.
Each Stratix IV device also has ATX PLLs that you can use in addition to the CMU
PLLs to generate the high-speed serial transceiver clock. The ATX PLLs also need
an input reference clock for operation. 6G ATX PLLs are available in both
Stratix IV GX and Stratix IV GT devices. 10G ATX PLLs are available only in
Stratix IV GT devices.
f
lists the terms used in the chapter.
For more information, refer to the “CMU Channel Architecture” section in
the
For more information, refer to the “Auxiliary Transmit (ATX) PLL Block”
and the “Transmitter Channel Datapath” sections in the
Transceiver Architecture
Stratix IV Transceiver Architecture
Stratix IV Transceiver Architecture
Stratix IV Transceiver Architecture
chapter.
chapter.
Description
2–8.
chapter.
chapter.
chapter.
Chapter 2: Stratix IV Transceiver Clocking
© March 2010 Altera Corporation
Stratix IV
Glossary of Terms
“Inter-
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