RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 109

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Datasheet
Next, the Multiplexer Section Termination (MST) function of the Receive Multiplexer Section
Processor (RMSP block) extracts the MSOH:
The MSA function of the Receive Multiplexer Section Processor (RMSP block) is to interpret the
H1-H3 payload point bytes to determine the location of the concatenated VC-3s or VC-4s payload
structure. Positive and negative pointer movement events are stored in counters that can be
accessed via the microprocessor interface. The data from the MSA section is then output to the
HPT section.
The Receive Higher order Path Processor (RHPP) extracts the HPOH:
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E1 is provided serially either at the RROW dedicated output or at the serial output bus RSOH.
F1 is provided serially at the RDOW dedicated output or at the RSOH output bus. In the case
of a dedicated serial ports, E1 and F1 are synchronous and can be accessed using the 64-KHz
clock provided at RROWC and the 8-KHz synchronization pulse provided at ROWBYC.
D1-D3 (DCC) are provided serially at the dedicated RRD output or at the RSOH output bus. In
the case of a dedicated serial port, the 192-KHz clock reference for this output is provided at
RRDC.
The other RSOH bytes are normally unused, and their value is provided serially at RSOH bus
output.
K1 and K2 bytes are provided via a microprocessor register. A filter based on 3 consecutive
identical values of K1 and K2 gates the update of the microprocessor registers. Those filtered
values are serially accessible at the Receive section Alarm port RSAL output. The received
value of K1 and K2 are also provided at the RSOH serial bus output. The detected K2-MS-
RDI alarm is accessible to the microprocessor via a maskable interrupt and provided serially at
RSAL output.
D4-D12 (DCC) are provided serially at the RMD dedicated output or at the RSOH output. In
the case of a dedicated serial access, the 576-KHz clock reference for this output is provided at
RMDC.
S1 filtered value is provided via a microprocessor register, and at the Receive Section Alarm
port RSAL serial output. A filter based on 3 consecutive identical values of S1 gates the
update of the microprocessor register. S1 received byte is also provided serially at RSOH.
M1 is provided serially at the RSOH output and updates MST REI counters accessible by the
microprocessor. The received MST REI is also provided serially at RSAL output.
E2 is provided serially at the dedicated RMOW output or at the RSOH output bus. In the case
of a dedicated serial output, the 64-KHz clock reference for this output is provided at ROWC
and the 8-KHz sync pulse at ROWBYC.
B2 byte is calculated internally and compared to the incoming B2 value. The errors are stored
into a set of counters that can be read by the microprocessor interface. These errors are also
inserted in the transmitted M1 byte if enabled (see register T_RMST_OP). Excessive Error
Defect (EED) and Degraded Signal Defect (DSD) fully configurable and independent BER
alarms thresholds are internally detected. Both detected encoded errors (generated MS REI)
and consecutive alarms are serially accessible at the Receive Section Alarm bus output
(RSAL).
The other MSOH bytes are normally unused, and their value is provided serially at RSOH
output.
The expected value of the 1-, 16-, or 64-byte J1 string is stored internally via the
microprocessor interface (Path Trace Buffer). The received J1 string is checked for stability,
compared with the stored version, and in the case of a 16-byte trace message, used to calculate
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