RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 278

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
11.6.2
278
15:11
10:0
Bit
4:3
Bit
5
2
1
0
AuPntrJustCnfg
ExpcAuPntrSS[1:0]
RcvMsaAisEn
RcvMsaAisFrc
AuPntrSSEn
Unused
RcvAUNegCnt[10:0]
R_AU_NCNT—Receive Negative AU Pointer Justification Event
Counter ((1cc)A1H)
This counter increments each time a positive pointer justification, on the receive side, is detected in
the H1: H2 bytes of the administrative unit payload. A write to the counter (register (1cc)A1H)
causes the entire counter to be loaded into a buffer and then cleared. The contents of the buffer can
then be read.
Name
Configures the justification rule (pointer increments/
decrements):
'1' = SONET Objective: When 8 of the 10 pointer bits are
detected with the I bits inverted and not the D bits, Au pointer
increments. If instead, the D bits are inverted and not the I
bits, it decrements.
'0' = SDH Objective: When 3 of the 5 pointer bits are
detected with the I bits inverted and not the D bits, Au pointer
increments. If instead, the D bits are inverted and not the I
bits, it decrements.
Bits [1:0] represent the expected value of the receive Au
Pointer SS two bits when AuPntrSSEn is enabled. For SDH,
set this to ‘10’ which is the expected value of the receive Au
Pointer SS two bits when AuPntrSSEn is enabled.
Controls automatic AIS generation from the MSA section to
the HPT section (see GenMsaAisSt bit (005H bit[5]) for AIS
generation logic):
'0' = Disables
'1' = Enables (SDH)
Forces AIS generation from the MSA section to the HPT
section via software:
'0' = Normal operation.
'1' = Forces AIS.
Enables consideration of AU pointer SS bits during pointer
processing. If enabled, the SS bits must be set to the
expected value ExpcAuPntrSS[1:0] or a LOP ((1cc)D2H[2])
alarm is generated. (SDH)
'0' = Disables
'1' = Enables
Bits [10:0] represent the count value.
Description
Description
Type
Type
R/W
R/W
R/W
R/W
R/W
R
Datasheet
Default
Default
00H
'00'
'0'
'0'
'0'
'0'