RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 96

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
2.1.4
2.1.5
96
Transmit ATM Cell Processor Block
Receive Byte-Synchronous HDLC Controller (Receive POS Block)
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The number of cells containing a correctable error in the header are counted in a 16-bit
counter.
The number of cells containing an uncorrectable error in the header are counted in a 16-bit
counter.
The number of accepted cells that have been lost due to a FIFO overflow are counted in a 16-
bit counter.
Maps ATM cells into the transmitted STS-48c/STM-16c/STS-48/STM-16/STS-12c/STM-4c/
STS-12/STM-4/STS-3c/STM-1/STS-1 signal.
Read control of four, independent, 32-cell deep, cell-rate decoupling, FIFO memories (Single
non-concatenated transceiver and Quad transceiver modes).
Read control of one, 256-cell deep, cell-rate decoupling, FIFO memory (Single concatenated
mode)
HEC generation/insertion.
Cell payload self-synchronous scrambling.
Idle cell insertion (cell rate decoupling process).
GFC cyclic halt function when configured as a controller device.
Unassigned cell insertion when configured as a controlled device.
The number of ATM cells that have been read from the transmit FIFO (assigned or unassigned
ATM Layer cells) are counted in a 24-bit counter.
The number of idle cells generated and mapped into the transmitted SONET/SDH frames are
counted in a 24-bit counter. It only counts the idle cells inserted by the cell rate decoupling
process, not the idle/unassigned cells inserted by the Generic Flow Control function.
Demaps byte-synchronous HDLC frames cells from the received STS-48c/STM-16c/STS-48/
STM-16/STS-12c/STM-4c/STS-12/STM-4/STS-3c/STM-1/STS-1 signal.
SPE self-synchronous descrambling before frame demapping.
FLAG-based HDLC frame delineation.
Control Escape stuffing removal (byte destuffing).
FCS-16/32 verification.
Optional HDLC Address and Control fields checking/dropping.
Programmable minimum and maximum packet lengths. Optional packet discarding based on
packet length.
Write control of four, independent, 2K-byte deep, packet-rate decoupling, FIFO memories
(Single non-concatenated transceiver and Quad transceiver modes).
Write control of one, 16K-byte deep, packet-rate decoupling, FIFO memory (Single
concatenated transceiver mode).
Datasheet