RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 221

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

11.2
11.2.1
11.2.2
Datasheet
(1cc)48H
(1cc)49H
(1cc)4AH
15:3
15:8
Bit
Bit
7:0
Table 26. Register Address Map (Sheet 6 of 6)
2
1
0
Address
Unused
BytChgUpdDsbl
CntrTest
MasIntEn
ChipVer[7:0]
ChipID[7:0]
Global Registers
MACNF—Microprocessor Access Configuration Register ((000)01H)
CHIP_ID—Chip ID and Version Numbers Register ((000)02H)
This register can only be read. It is used to identify the version of the chip.
Name
Name
T_PFUCNT
T_POSINT
T_POSINTEN
Mnemonic
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
This bit controls received byte register updates when a register’s
byte change interrupt is active. This bit is generally used for
diagnostics. For example, if the received K2 byte were rapidly
toggling, the values that it is toggling between could be captured by
setting this bit:
'0' = Enable received byte register updates when byte change
interrupt is active.
'1' = Disable received byte register updates when byte change
interrupt is active.
This bit should always be set to '0' during normal operation. It
allows faster testing of the overflow interrupt functionality during
simulation:
'0' = Normal operation
'1' = Set overflow count:
B1 counter = 7
B2 bit counter = 31
B2 block counter = 3
M1 REI bit counter = 31
M1 REI block counter = 3
B3 bit/block counters = 7
G1 REI bit/block counters = 7
This bit controls the chip interrupt pin:
'0' = Disable interrupt pin.
'1' = Activate interrupt pin when there are unmasked active
interrupts.
Chip Version: This field contains the Intel IXF6048 version number.
Chip Identification: This field contains the Intel IXF6048
Identification number.
Transmit POS Interrupt Enable
Transmit Packet FIFO Underflow Counter
Transmit POS Interrupt Register
Description
Description
Register Name
Type
Type
R/W
R/W
R/W
R
R
Type
R/W
R
R
Default
Default
02H
01H
Page #
'0'
'0'
'0'
0
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324
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