RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 226

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
226
Bit
2:0
6
5
4
3
QMode
CMode
UOutEn
OutEn
UAddrBase[2:0]
Name
QMode configures Intel IXF6048 as a Single or Quad transceiver.
QMode configures the Line Side Interface I/O as a Single Line Side
Interface or as four independent Serial Line Side Interfaces:
'0' = Single transceiver mode. Single OC-48c/48nc/12c/12nc/3c/3nc/
1.
'1' = Quad transceiver mode. Quad (in other words, more than one)
OC-12c/3c/1. CMode must be set to ‘1’.
CMode configures Intel IXF6048 as a concatenated or non-
concatenated processor. CMode is used only when the Intel
IXF6048 is configured as a Single transceiver (QMode = '0'):
'0' = Intel IXF6048 is configured as a non-concatenated processor
(Single STS-48/STM-16, STS-12/STM-4, or STS-3).
'1' = Intel IXF6048 is configured as a concatenated processor
(Single STS-48c/STM-16c).
UOEn enables the UTOPIA interface:
'0' = All the UTOPIA interface outputs (RXDATA, etc.) are held in
high impedance.
'1' = All the UTOPIA interface outputs operate in normal mode.
In order to avoid collisions that could damage the device when
several PHY devices are connected into the same UTOPIA
interface, the software MUST configure the UTOPIA interface
(physical address of the device, decode-response delay, ATM/
POS, etc.) before setting UOEn to logic one.
UOutEn is internally ORed with the UOEN input.
This bit controls all the output pins of Intel IXF6048 except the
microprocessor interface:
'0' = All the Intel IXF6048 outputs (except microprocessor interface)
are held in high impedance.
'1' = All the Intel IXF6048 outputs operate in normal mode.
In order to avoid collisions that could damage the device when
several PHY devices are connected into the same UTOPIA
interface, the software must configure the UTOPIA interface
(physical address of the device, decode-response delay, ATM/
POS mode, etc.) before setting IOBusEn to logic one.
OutEn is internally ORed with the OEN input.
UAddrBase[2:0] are the device identification address and contains
the address of the memory space that Intel IXF6048 occupies in the
UTOPIA interface. UAddrBase[2:0] are compared with
RXADDR[4:2] and TXADDR[4:2]. The least significant two bits of
the address (RXADDR[1:0]) are hard-wired to select a specific
channel ('00' = channel 0, '01' = channel 1, '10' = channel 2, '11' =
channel 3). The address value 1FH is the null physical address and
can not be assigned to any PHY port.
Description
Type
R/W
R/W
R/W
R/W
R/W
Datasheet
Default
'000'
'0'
'1'
'0'
'0'