RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 223

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

11.2.4
11.2.5
Datasheet
15:12
15:12
11:8
11:8
Bit
7:4
3:0
Bit
7:4
3:0
Unused
BfrRcvSdh[3:0]
BfrXmtAtmPos[3:0]
BfrRcvAtmPos[3:0]
RcvHptInt[3:0]
RcvAdpInt[3:0]
RcvMuxInt[3:0]
RcvRegInt[3:0]
BUF_ACNTS—Buffer All Counters Global Register ((000)04H)
Writing a logic one in any of these bits causes all of the counters in the corresponding processor to
be loaded into buffers and then cleared. The contents of an individual counter buffer can then be
read at the addresses specified for the counters in this document. Counters can be individually
buffered by writing to the specified MSByte of the desired counter. Writing a logic zero has no
effect on the corresponding processor.
SDH_GIS—SDH Global Interrupt Source Register ((000)05H)
This register indicates that an SDH interrupt source register on channel #i (i = 0, 1, 2, 3) contains
an active interrupt. Each bit in this register is active-high and represents the logic OR of all the
interrupt bits in the associated channel interrupt source register. Each bit in this register clears upon
reading the associated channel interrupt source register.
Name
Name
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
BfrRcvSdh[i] (i = 0, 1, 2, 3) loads into buffers and clears all the
counters of the receive SDH processor on channel #i.
BfrXmtAtmPos[i] (i = 0, 1, 2, 3) loads into buffers and clears all
the counters of the transmit ATM/POS processors on channel #i.
BfrRcvAtmPos[i] (i = 0, 1, 2, 3) loads into buffers and clears all
the counters of the receive ATM/POS processors on channel #i.
RcvHptInt[i] (i = 0, 1, 2, 3) indicates that one or more
interrupt bits are active in the IS_HPT register on channel
#i.
RcvAdpInt[i] (i = 0, 1, 2, 3) indicates that one or more
interrupt bits are active in the IS_ADP register on channel
#i.
RcvMuxInt[i] (i = 0, 1, 2, 3) indicates that one or more
interrupt bits are active in the IS_MUX register on channel
#i.
RcvRegInt[i] (i = 0, 1, 2, 3) indicates that one or more
interrupt bits are active in the IS_RG register on channel
#i.
Description
Description
Type
Type
W
W
W
R
R
R
R
Default
Default
'XXXX'
'XXXX'
'XXXX'
'XXXX'
'XXXX'
'XXXX'
'XXXX'
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