RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 155

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

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Datasheet
Transmit multiplex & regenenerator Section OverHead Serial Orderwire Timing (E1, F1, and E2)
TOWC
TOWBYC
TROW
TDOW
TMOW
Receive multiplex & regenenerator Section OverHead Serial Orderwires Timing (E1, F1, and E2)
ROWC
ROWBYC
RROW
RDOW
RMOW
Figure 25. Transmit Orderwire E1, E2, and F1 Timing
Figure 26. Receive Section Orderwire E1, F1, and E2 Timing
Output clock
(64 KHz)
Input E1
data channel
Input F1
data channel
Input E2
data channel
Output clock
(64 KHz)
Output E1
data channel
Output F1
data channel
Output E2
data channel
Output frame byte
clock (8 KHz)
Output frame byte
clock (8 KHz)
4.5.5.3.2 Receive Side Access (i = 0, 1, 2, 3)
— Data outputs are RROW[i], RMOW[i], and RDOW[i].
— Clock reference is ROWC[i]. This 64-KHz signal is a square wave. Its phase, relative to
— Byte reference is ROWBYC[i]. By default, it is active-high on the MSB of each byte (see
— Both the clock reference and the byte reference are synchronous with the receive clock.
E1 LSB
E2 LSB
F1 LSB
E1 LSB
F1 LSB
E2 LSB
Configuration bit OWPlsCnf = 0 (register OHPCNF) and configuration bit Pol_TOWC = 0 (register OCPCNF)
the data transition, may be inverted via global configuration register OCPCNF, bit
Pol_ROWC.
Figure
configuration register OHPCNF, bit OWPlsCnf).
Configuration bit OWPlsCnf = 0 (register OHPCNF) and configuration bit Pol_ROWC = 0 (register OCPCNF)
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
E1 MSB
F1 MSB
E2 MSB
E1 MSB
F1 MSB
E2 MSB
26). However, it may be configured so that it is active on the LSB (see global
E1 bit 6
F1 bit 6
E2 bit 6
E1 bit 6
F1 bit 6
E2 bit 6
E1 bit 5
F1 bit 5
E2 bit 5
E1 bit 5
F1 bit 5
E2 bit 5
1 frame : 125 µs
E1 bit 4
F1 bit 4
E2 bit 4
E1 bit 4
F1 bit 4
E2 bit 4
1 frame : 125 µs
E1 bit 3
F1 bit 3
E2 bit 3
E1 bit 3
F1 bit 3
E2 bit 3
E1 bit 2
E2 bit 2
F1 bit 2
E1 bit 2
F1 bit 2
E2 bit 2
E1 bit 1
F1 bit 1
E2 bit 1
E1 bit 1
F1 bit 1
E2 bit 1
E1 LSB
F1 LSB
E2 LSB
E1 LSB
F1 LSB
E2 LSB
E1 MSB
E2 MSB E2 bit 6
F1 MSB
E1 MSB E1 bit 6
E2 MSB E2 bit 6
F1 MSB F1 bit 6
E1 bit 6
F1 bit 6
E1 bit 5
E2 bit 5
F1 bit 5
E1 bit 5
F1 bit 5
E2 bit 5
E1 bit 4
F1 bit 4
E2 bit 4
E1 bit 4
F1 bit 4
E2 bit 4
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