RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 94

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
2.1.2
94
SONET/SDH Transmitter Block
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•Programmable Expected Signal label (C2 byte).
K1, K2 (APS), S1 (synchronization message status), and C2 (path Signal Label) received
bytes filtering; parallel access (via microprocessor) and serial access (via Receive Section
serial Alarm bus: RSAL output).
Full J0 and J1 (Trace Identifiers) processing programmable as a 1-, 16- (with CRC-7), or 64-
byte trace. Programmable expected J0 and J1 traces, and parallel access to the received
accepted J0 and J1 traces.
BIP/Block error detection and count for: B1 (regeneration section BIP-8), B2 (multiplexer
section BIP-8/24/96/392), and B3 (path layer BIP-8). Demultiplexing and BIP/Block error
count of the received Multiplexer Section Remote Error Indication (MS-REI in M1 byte), and
received Path layer Remote Error Indication (HP-REI in G1 byte). Pointer justification events
count (positive and negative).
The Data Communication Channels (D1-D3, D4 to D12), the Section Orderwires (E1 and E2),
and the user channel (F1) are all demultiplexed and then output either on the dedicated serial
ports (at 192 Kbit/s 576 Kbit/s) or on the Receive Section serial OverHead bus (RSOH).
The Section Orderwires (E1 and E2) and user channel (F1) are both demultiplexed and then
extracted either on the dedicated serial ports (at 64 Kbit/s) or on the Receive Section serial
OverHead bus (RSOH).
The Path Orderwires (F2 and F3) are demultiplexed and extracted either on the dedicated
serial ports (at 64 Kbit/s) or on the Receive Path serial OverHead bus (RPOH).
Serial access to all receive section overhead bytes via either a 1.728 Mbit/s bus (OC-1), a
5.184 Mbit/s bus (OC-3c), a 20.736 Mbit/s bus (OC-12c), or 4 × 20.736 Mbit/s busses (OC-
48): (RSOH).
Serial access to all the receive path overhead bytes via a 576-Kbit/s bus: (RPOH).
Serial access to all the receive section and path alarms, generated remote indications, and error
count, output on two 576-Kbit/s buses (RSAL and RPAL).
Programmable in repeater or demultiplexer mode.
Insertion of microprocessor programmable 1-, 16- (with CRC-7), or 64-byte Trace Identifier
(J1 byte) and Signal Label (C2 byte).
Insertion of path Remote Defect and Error Identification (HP-RDI—enhanced or not—and
HP-REI in G1 byte) either via automatic feedback from the receive, via the Transmit Path
serial input Alarm port (TPAL), or via the microprocessor.
Path BIP-8 (B3 byte) calculation and insertion.
Serial access and insertion of any POH bit via the Transmit Path OverHead bus input (TPOH).
Microprocessor fully programmable transmit pointer value insertion (H1, H2).
Insertion of section Remote Defect and Error Identification (MS-RDI—enhanced or not—and
MS-REI in both K2 and M1 bytes) either via automatic feedback from the receive, via the
Transmit Section serial input Alarm port (TSAL), or via the microprocessor.
Insertion of APS bytes (K1, K2) and synchronization byte (S1) either from the serial insertion
port or from micro-processor programming.
Datasheet