RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 281

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

11.7
11.7.1
Datasheet
15:14
Bit
13
12
11
10
9
8
7
HptRdiDetCnt[1:0]
HptRdiDetEnhCnfg
C2MsMtchCnt
HpSlmOnC2UnstableEn
B3CntrCnfg
HptReiCntrCnfg
RcvStuffCnfg
HptRdiOnLcdEn
SONET/SDH Receive High-Order Path Termination Channel
Registers
R_HPT_C1—Receive HPT Configuration 1 Register ((1cc)A4H)
Name
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
These bits configure the number of received G1 bytes that must have the
same value in the RDI bit(s) for the HptRdiSt bit(s)/alarm (register
R_HPT_RDI bit[3:1]) to be updated. The received G1 RDI bits + spare can
be retrieved via register R_HPT_RDI bit[3:0]. Note that if received RDI is
not enhanced (see RcvHptRdiDetEnh), only bit #3 of G1 is considered in
the algorithm:
'11' = 16 received G1 bytes
'10' = 10 received G1 bytes (SDH)
'01' = 5 received G1 bytes (SDH)
'00' = 3 received G1 bytes (SDH)
Configures the detection of received HPT RDI (considered enhanced or
not):
'0' = Non-enhanced Received G1 RDI bits.
'1' = Enhanced Received G1 RDI bits.
Configures the number of mismatches, between the RcvC2 byte (register
R_C2) and the ExpcC2 byte ((1cc)A6H), needed for the HptSlmSt bit
(register S_HPT bit[12]) to be updated (SDH):
'0' = 3 mismatches.
'1' = 5 mismatches.
This bit configures the setting of the Hp-Slm alarm i.e., HptSlmSt, when the
receive C2 Signal Label is unstable:
'1' = Active C2UnstableSt alarm forces the HptSlmSt alarm (Hp-Slm).
'0' = HptSlmSt (Signal Label Mismatch) alarm and C2UnstableSt alarm are
two independent processes.
Configures whether the B3 error counter updates using bit errors or block
errors:
'0' = Bit errors.
'1' = Block errors.
Configures whether the HPT REI error counter (register HPTREI_CNT)
updates using bit errors or block errors:
'0' = Bit errors.
'1' = Block errors.
In STS-1/STM-0 mode, this bit configures whether the two fixed stuff
columns (#30 and #59) are part of the payload:
'1' = Columns #30 and #59 of the SPE are not part of the payload and
considered as stuff columns.
'0' = Columns #30 and #59 of the SPE are part of the payload and their
contents are part of the B3 BIP calculation.
Enables the insertion of HPT RDI on active AtmLcdSt (H[bit]) alarm (ATM
Loss Of Cell Delineation):
'0' = Active AtmlcdSt alarm does not cause insertion of RDI bits into the
transmitted G1 byte.
'1' = Active AtmlcdSt alarm causes insertion of RDI bits into the transmitted
G1 byte (payload defect).
Description
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
'01'
'1'
'0'
'0'
'0'
'0'
'0'
'1'
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