RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 177

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

6.5
Datasheet
Figure 49
PHY device. This could be for a single OC-3/12/48 non-concatenated line side input or four OC-1/
3/12 concatenated line side inputs. This example corresponds to the following configuration:
Figure 51
device. This could be for a single OC-3/12 non-concatenated line side input or four OC-1/3
concatenated line side inputs. This example corresponds to the following configuration:
Figure 53
mode. This could be for a single OC-3/12 non-concatenated line side input or four OC-1/3
concatenated line side inputs. This example corresponds to the following configuration:
ATM-UTOPIA Level 3/Level 2 Compatibility
Intel IXF6048 operates according to the ATM Forum UTOPIA Level 3 specification by using the
following settings:
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XmtUWidth[1:0] = '10' (32-bit interface)
XmtCellStruct = '1' (14-word cell data structure)
XmtDRCnf = '1' (2 clock cycle decode-response time)
XmtMPhyDevCnf = '0' (single PHY device)
XmtUQuad = '0' (single interface)
XmtUWidth[1:0] = '10' (32-bit interface)
XmtCellStruct = '1' (14-word cell data structure)
XmtDRCnf = '1' (2 clock cycle decode-response time)
XmtMPhyDevCnf = '1' (multiple PHY device)
XmtUQuad = '0' (single interface)
XmtUWidth[1:0] = '01' (16-bit interface)
XmtCellStruct = '1' (27-word cell data structure)
XmtDRCnf = '0' (1 clock cycle decode-response time)
XmtMPhyDevCnf = '0' (single PHY device)
XmtUQuad = '0' (single interface)
XmtUWidth[1:0] = '01' (16-bit interface)
XmtCellStruct = '1' (27-word cell data structure)
XmtDRCnf = '0' (1 clock cycle decode-response time)
XmtMPhyDevCnf = '1' (multiple PHY device)
32-bit data bus
52-byte or 56-byte ATM cell data structure
2 clock cycles decode-response configuration
Single-device mode
shows an example where the transmit interface has been configured as a 32-bit multiple
shows an example where the transmit interface has been configured as a 16-bit single
shows an example where the transmit interface has been configured in UTOPIA Level 2
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
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