RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 62

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
62
Table 4.
Pin Description (Sheet 48 of 66)
TXENB_0
TXENB_1
TXENB_2
TXENB_3
TXSOF_0
TXSOF_1
TXSOF_2
TXSOF_3
TXEOF_0
TXEOF_1
TXEOF_2
TXEOF_3
TXPRTY_0
TXPRTY_1
TXPRTY_2
TXPRTY_3
TXERR_0
TXERR_1
TXERR_2
TXERR_3
NOTE: See notes 1, 2, and
Pin Name
Pin
D9
M6
H6
C2
H1
G2
G5
H4
D1
C4
F9
B8
E9
K5
F6
E6
K4
E3
J2
J5
LVTTL
Input
LVTTL
Input
LVTTL
Input
LVTTL
Input
LVTTL
Input
Type
3
at the end of the table.
Transmit Write Enable. TXENB_i (i = 0, 1, 2, 3) is the active-low
transmit enable that controls write access to transmit interface #i.
TXENB_i (i = 0, 1, 2, 3) is sampled on the rising edge of TXCLK_i.
Transmit Start-of-Frame. TXSOF_i (i = 0, 1, 2, 3) (active-high) marks
the first byte of a frame (cell or packet) in TXDATA_i[7:0].
TXSOF_i (i = 0, 1, 2, 3) is sampled on the rising edge of TXCLK_i.
Transmit End-of-Frame. TXEOF_i (i = 0, 1, 2, 3) (active-high) marks the
last byte of a frame (cell or packet) in TXDATA_i[7:0]. TXEOF_i is used
only in POS mode; in ATM mode, TXEOF_i is an unused input.
TXEOF_i (i = 0, 1, 2, 3) is sampled on the rising edge of TXCLK_i.
Transmit Data Parity. TXPRTY (i = 0, 1, 2, 3) indicates the parity of
TXDATA_i[7:0]. Either odd or even parity is selectable (see XmtPrtyCnf
in register T_UICHCNF).
TXPRTY_i (i = 0, 1, 2, 3) is sampled on the rising edge of TXCLK_i.
Transmit Packet Error. TXERR_i (i = 0, 1, 2, 3) is an active-high input
allowing the Data Link Layer device to indicate that the current packet
must be aborted (transmitted ending with an Abort sequence). TXERR_i
is used only in POS mode; in ATM mode, TXERR_i is an unused input.
After asserting TXERR_i (i = 0, 1, 2, 3), the next word written into
transmit FIFO #i should be the first word of the next packet (TXSOF_i
asserted). After asserting TXERR_i, the writings to transmit FIFO #i are
ignored until a start-of-frame (TXSOF_i asserted) is detected. When
TXERR_i is asserted, both TXSOF_i and TXEOF_i are ignored.
TXERR_i (i = 0, 1, 2, 3) is sampled on the rising edge of TXCLK_i.
• When TXENB_i (i = 0, 1, 2, 3) is deasserted, nothing happens on
• When TXENB_i (i = 0, 1, 2, 3) is asserted, the transmit FIFO #i is
interface #i.
written.
Description
Datasheet