RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 159

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

5.1
5.1.1
Datasheet
Receive ATM Cell Processing
When Intel IXF6048 is configured as a Quad transceiver (STS-1/STS-3c/STM-1/STS-12c/STM-
4c) or as a Single OC-48/STM-16/STM-4 (non-concatenated) transceiver, each of the four receive
ATM cell processors (RACP) extracts the incoming ATM cells from the corresponding SPE and
writes them into a FIFO memory. The FIFO memory is 256-cell deep in the first channel and 32-
cell deep in the other three channels.
When Intel IXF6048 is configured as a Single OC-48c/STM-12c (concatenated) transceiver, only
one RACP is active, extracting the incoming ATM cells from the SPE and writing them into a 256-
cell deep FIFO memory.
HEC-Based Cell Delineation
The RACP performs cell delineation based on HEC correct calculations in accordance with ITU-T
I.432. Intel IXF6048 offers some additional optional features to this standard process. The
following describes the Intel IXF6048 cell delineation process.
The HEC is a CRC-8 calculation over the first 4 bytes of the ATM cell header based on the
polynomial X
received HEC octet before checking. While searching for the cell boundary location, the RACP is
in the HUNT state. In this state, the RACP checks one of the 53 possible boundary candidates (per-
byte checking). When a correct HEC is found (a cell header candidate), the RACP enters the
PRESYNC state.
The PRESYNC state validates the cell boundary location detected in the HUNT state. If no HEC
errors are detected during DELTA consecutive cells (cell-by-cell checking), the SYNC state is
entered.
While in the SYNC state, synchronization is maintained until ALPHA consecutive incorrect HECs
are detected. The values of ALPHA and DELTA, determining the robustness against false
misalignments and false delineations, are ALPHA = 7 and DELTA = 6.
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
8
+ X
2
+ X + 1. The co-set polynomial X
6
+ X
4
+ X
2
+ 1 ('01010101') is added to the
159