RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 8

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Contents
8
68 Receive POS-UTOPIA Interface as a Multiple PHY Device with 64-Bit Data Bus
69 Transmit POS-UTOPIA Interface as a Multiple PHY Device with 64-Bit Data Bus
70 Receive POS-UTOPIA Interface as a Single PHY Device with 32-Bit Data Bus Using
71 Transmit POS-UTOPIA Interface as a Single PHY Device with 32-Bit Data Bus Using
72 Receive POS-UTOPIA Interface as a Multiple PHY Device with 32-Bit Data Bus
73 Transmit POS-UTOPIA Interface as a Multiple PHY Device with 32-Bit Data Bus
74 Receive POS-UTOPIA Interface as a Multiple PHY Device with 16-Bit Data Bus
75 Transmit POS-UTOPIA Interface as a Multiple PHY Device with 16-Bit Data Bus
76 Receive POS-UTOPIA Interface as a Single PHY Device with 16-Bit Data Bus Using
77 Transmit POS-UTOPIA Interface as a Single PHY Device with 16-Bit Data Bus Using
78 Receive 16-bit Differential PECL Line Side Interface Timings ................................................. 328
79 Transmit 16-Bit Differential PECL Line Side Interface Timings ................................................ 329
80 Receive 1-Bit Differential PECL Line Side Interface Timings ................................................... 330
81 Transmit 1-bit Differential PECL Line Side Interface Timings .................................................. 331
82 Receive 32-Bit TTL Line Side Interface Timings ...................................................................... 332
83 Transmit 32-Bit TTL Line Side Interface Timings ..................................................................... 333
84 Receive 8-Bit TTL Line Side Interface Timings ........................................................................ 334
85 Transmit 8-Bit TTL Line Side Interface Timings ....................................................................... 335
86 Serial Overhead Timing Diagram ............................................................................................. 336
87 Receive UTOPIA Single Interface Configured for 104 MHz Operation: 32/16/8-Bit
88 Transmit UTOPIA Single Interface Configured for 104 MHz Operation: 32/16/8-Bit
89 Receive UTOPIA Quad Interface Configured for 104 MHz Operation: 8-Bit Data Bus,
90 Transmit UTOPIA Quad Interface Configured for 104 MHz Operation: 8-Bit Data
91 Receive UTOPIA Single Interface Configured for 50 MHz Operation: 64/32/16/8-Bit
92 Transmit UTOPIA Single Interface Configured for 50 MHz Operation: 64/32/16/8-Bit
93 Receive UTOPIA Quad Interface Configured for 50 MHz Operation: 16/8-Bit Data
94 Transmit UTOPIA Quad Interface Configured for 50 MHz Operation: 16/8-Bit Data
95 Microprocessor Read Timing.................................................................................................... 343
96 Microprocessor Write Timing .................................................................................................... 344
97 Asynchronous Reset (RESET) Timing ..................................................................................... 345
98 JTAG Test Circuitry .................................................................................................................. 347
99 TAP State Machine................................................................................................................... 347
100 Boundary Scan Cell Types ....................................................................................................... 349
101 Mechanical Information for the 600 TBGA (Top View) ............................................................. 350
Using Port Selection (POS-UTOPIA Level 3 Mode) ................................................................. 207
Using Port Selection (POS-UTOPIA Level 3 Mode) ................................................................. 207
Port Selection (POS-UTOPIA Level 3 Mode) ........................................................................... 208
Port Selection (POS-UTOPIA Level 3 Mode) ........................................................................... 208
Using Port Selection ................................................................................................................. 209
Using Port Selection ................................................................................................................. 209
Using Port Selection (POS-UTOPIA Level 2 Mode) ................................................................. 210
Using Port Selection (POS-UTOPIA Level 2 Mode) ................................................................. 210
Port Selection ........................................................................................................................... 211
Port Selection ........................................................................................................................... 211
Data Bus, Two Clock Cycle Decode-Response Delay and No High-Impedance Outputs ....... 337
Data Bus, Two Clock Cycle Decode-Response Delay and No High-Impedance Outputs ....... 337
Two Clock Cycle Decode-Response Delay and No High-Impedance Outputs ........................ 338
Bus, Two Clock Cycle Decode-Response Delay and No High-Impedance Outputs ................ 339
Data Bus and One/Two Clock Cycle Decode-Response Delay Signals .................................. 340
Data Bus and One/Two Clock Cycle Decode-Response Delay Signals .................................. 340
Bus and One/Two Clock Cycle Decode-Response Delay ........................................................ 341
Bus and One/Two Clock Cycle Decode-Response Delay ........................................................ 342
Datasheet