RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 126

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
126
In addition, for the support of “supervisory unequipped”, it is possible to disable HP-RDI
generation and/or AIS generation because of the Unequipped (C2 = all '0's) detection, via
configuration register R_HPT_C2. In this case, the HP-TIM alarm would trigger both HP-RDI and
AIS generation instead of the detected Unequipped (C2 = all '0's).
4.4.1.6.5 G1 Byte
This byte conveys the path status and performance back to a VC-Nc trail termination source as
detected by a trail termination sink.
G1[7:4] bits act as a Remote Error Indication (REI). They report the number of B3 errors detected
at the remote end. These REI errors are accumulated in the REI counter register HPTREI_CNT.
The REI counter can be selected as a bit counter or as a block counter via register R_HPT_C1.
G1[3:1] bits act as a Remote Detection Indication (RDI). They, along with G1[0] (spare bit), are
accessible via register R_HPT_RDI. The contents of this register is filtered over 3, 5, 10, or 16
frames, configurable via register R_HPT_C1. An update to register R_HPT_RDI is indicated in
register IS_HPT. It is possible to configure the receive path RDI as non enhanced (see register
R_HPT_RDI), so that update and detection of the path RDI is only based on G1[3] bit.
The receive path REI bits and filtered value of receive RDI are serially accessible at the RPAL
serial alarm bus output and the receive G1 byte is serially accessible at RPOH bus output pin.
An RDI is reported to the far-end upon detection of an LOP, AU-AIS, TIM (J1 Mismatch), SLM
(C2 Mismatch), unequipped alarm, or an LCD (Loss Of ATM Cell Delineation). The dependency
and coding of RDI on either of these conditions is configurable via R_HPT_C1 (generated RDI as
enhanced or non enhanced). This ensures compatibility of the new equipment with an installed
equipment base. (See
and serially accessible at the RPAL serial alarm bus output.
4.4.1.6.6 F2 Byte (Optional)
This 64-Kbit/s channel is used for optional user purposes and can be used as an extra maintenance
orderwire channel. The data is accessible via RPOW1. The 64-KHz clock and the 8-KHz byte
synchronization signals are also used to receive the F3 byte and are provided at pins RPOWC and
RPOWBYC. Note that the access to this channel is limited in quad processor mode (due to pin
count).
The receive F2 byte may be also serially accessible at RPOH bus output pin.
4.4.1.6.7 F3/Z3 Byte (Optional)
This 64-Kbit/s channel is used for optional user purposes and can be used as extra maintenance
orderwire channel. The data is accessible via RPOW2. The 64-KHz clock and the 8-KHz byte
synchronization signals are used to receive also the F2 byte and are provided at pins RPOWC and
RPOWBYC. Note that the access to this channel is limited in quad processor mode (due to pin
count).
•
•
•
•
C2 equal to all '0's (Unequipped)
First byte of the J1 accepted trace is equal to all '0's
J1 trace correct or incorrect (J1 Mismatch/Unstable)
B3 detected BIP/Block errors (B3 error counter)
Table
14). The generated RDI bits are so internally looped to the transmitter
Datasheet