RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 282

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
11.7.2
282
Bit
6:5
2:1
15:14
4
3
0
Bit
13
12
HptRdiOnSlmEn[1:0]
HptRdiOnTimEn
HptRdiOnUnEqpEn
HptRdiGenEnhCnfg[1:0]
G1SpOnRpalCnfg
Unused
HpTimOnCRC7ErrDsb
HpTimOnUnstableEn
R_HPT_C2—Receive HPT Configuration 2 Register ((1cc)A5H)
Name
Name
Enables and configures the insertion of HPT RDI on active HptSlmSt (i63H
bit[12]) alarm:
'0X' = Active HptSlmSt alarm does not cause insertion of RDI bits into the
transmitted G1 byte.
'10' = Active HptSlmSt alarm causes insertion of RDI bits into the
transmitted G1 byte as a connectivity defect.
'11' = Active HptSlmSt alarm causes insertion of RDI bits into the
transmitted G1 byte as a payload defect.
Enables the insertion of HPT RDI on active HptTimSt (i63H bit[15]) alarm:
'0' = Active J1MsMtchSt (TIM) alarm does not cause insertion of RDI bits
into the transmitted G1 byte.
'1' = Active J1MsMtchSt (TIM) alarm causes insertion of RDI bits into the
transmitted G1 byte (connectivity defect).
Enables the insertion of HPT RDI on active HptUnEqpSt (i63H bit[13])
alarm:
'0' = Active HptUnEqpSt alarm does not cause update of transmitted G1
RDI bits
'1' = Active HptUnEqpSt alarm causes update of transmitted G1 RDI bits
(connectivity defect).
Configures the generation of HPT RDI (enhanced or not) at both the RPAL
bus output and the internal feedback value to the transmitter:
'00' = Non-enhanced generated G1 RDI bit. (RDI = '100'—no RDI = '000').
'01' = Non-enhanced generated G1 RDI bit. (RDI = '111'—no RDI = '011').
(SDH)
'1X' = Enhanced generated G1 RDI bit (refer to
RDI bit coding). (SDH)
Sets the value of G1 Spare Bit (G1[0]) at the RPAL output (Serial Receive
Path Alarm Port):
'0' = Value is set to '0'. (SDH)
'1' = Value is set to '1'.
This bit configures the setting of the Hp-Tim alarm i.e.,
J1MsMtchSt, when the CRC-7 is wrong:
'1' = An active J1Crc7ErrSt alarm masks the J1MsMtchSt
alarm (Hp-Tim), if (HpTimOnUnstableEn is low) or
(HpTimOnUnstableEn is high and J1UnstableSt is low).
'0' = J1MsMtchSt (Hp-Tim) alarm and J1CRC7ErrSt alarm
are two independent processes.
This bit configures the setting of the Hp-Tim alarm i.e.,
J1MsMtchSt, when the trace is unstable:
'1' = An active J1UnstableSt alarm forces the J1MsMtchSt
alarm (Hp-Tim).
'0' = J1MsMtchSt (Hp-Tim) alarm and J1UnstableSt alarm
are two independent processes.
Description
Description
Table 15
for the Enhanced
Type
R/W
R/W
Type
R/W
R/W
R/W
R/W
R/W
Datasheet
Default
Default
'0'
'0'
'10'
'11'
'1'
'1'
'0'