RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 270

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
11.5.5
270
31:17
31:21
16:0
20:0
Bit
Bit
Unused
MstReiBlkCnt[16:0]
Unused
MstReiBipCnt[20:0]
This counter increments every frame in which the value of MST REI bits (M1[7:0]) is nonzero. A
write to the MSByte of the counter (register (1cc)9AH) causes the entire counter to be loaded into a
buffer and then cleared. The contents of the buffer can then be read.
MR_BIPCNT—MST REI BIP Error Counter ((1cc)9CH-(1cc)9BH)
(1cc)9CH = Bits[23:16], (1cc)9BH = Bits[15:0] (16-bit access only).
Every frame, the value of MST REI bits (M1[7:0]) is added to this counter. A write to the MSByte
of the counter (register (1cc)9CH) causes the entire counter to be loaded into a buffer and then
cleared. The contents of the buffer can then be read.
When operating in concatenated mode, the received M1 overhead values (in the third STS-1/STM-
0) are accumulated in the specific port/channels M1 accumulation register—one MR_BIPCNT
register per port/channel. For example, if you were using port/channel 0 then the MR_BIPCNT
register to use would be at address 0x[0100b]9Ch~0x[0100b]9Bh or 0x49Ch~0x49Bh. If you were
using port/channel 3 then you would use the MR_BIPCNT register at address
0x[0111b]9Ch~0x[0111b]9Bh or 0x79Ch~0x79Bh.
When operating in non-concatenated STS-3 and STS-12/STM-4 modes, the received M1 overhead
values (in the third STS-1/STM-0) are accumulated in channel 2’s MR_BIPCNT register (address
0x[0110b]9Ch~0x[0110b]9Bh or 0x69Ch~0x69Bh) only. Channel 0, 1 and 3’s MR_BIPCNT
registers would not be used. This applies when receiving 1xOC-3nc (which equates to three STS-
1’s and which can only use the line side port 0) or 1xOC-12nc (which equates to four STS-3c’s and
which can only use the line side port 0).
When operating in non-concatenated STS-48/STM-16 mode, the received M1 overhead values (in
the third STS-1/STM-0) are accumulated in port/channel 0’s M1 accumulation register. The
MR_BIPCNT register to use would be at address 0x[0100b]9Ch~0x[0100b]9Bh or
0x49Ch~0x49Bh.
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