RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 28

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
28
Table 4.
Pin Description (Sheet 14 of 66)
TPDO_0[0]
TPDO_0[1]
TPDO_0[2]
TPDO_0[3]
TPDO_0[4]
TPDO_0[5]
TPDO_0[6]
TPDO_0[7]
TPDO_1[0]
TPDO_1[1]
TPDO_1[2]
TPDO_1[3]
TPDO_1[4]
TPDO_1[5]
TPDO_1[6]
TPDO_1[7]
TPDO_2[0]
TPDO_2[1]
TPDO_2[2]
TPDO_2[3]
TPDO_2[4]
TPDO_2[5]
TPDO_2[6]
TPDO_2[7]
TPDO_3[0]
TPDO_3[1]
TPDO_3[2]
TPDO_3[3]
TPDO_3[4]
TPDO_3[5]
TPDO_3[6]
TPDO_3[7]
TPCI_0
TPCI_1
TPCI_2
TPCI_3
NOTE: See notes 1, 2, and
Pin Name
AG5
AG3
AG2
AG1
AH4
AE6
AE5
AH1
AE4
AD5
AB6
AC5
AB5
AD4
AC4
AE2
AE1
AB4
AC2
AD1
AB3
AC1
AD6
AA5
AB1
AF6
AJ4
AJ2
AF5
AJ1
AF4
AF3
AF1
Pin
W6
Y6
Y5
Transmit 622/155/51 Mbit/s TTL Quad Parallel Line Side Interface
LVTTL
Input
12 mA
LVTTL
Input
Type
3
at the end of the table.
Transmit Parallel Data Output TTL
The transmit TTL quad parallel line side interface provides low speed
connection (≤ 77.76 MHz) to 622/155/51 Mbit/s multiplexers.
The quad 8-bit mode can be used when Intel IXF6048 is configured as a
Quad STS-12c/STM-4c/STS-3c/STM-1/STS-1/STM-0 transceiver.
TPDO_i[7:0] (i = 0, 1, 2, 3) carries the outgoing 622/155/51 Mbit/s data
stream in byte format for channel #i. TPDO_i[7] is the MSB (first
transmitted bit) and TPDO_i[0] is the LSB (last transmitted bit). Connect
pin[7] to the MSB of the serializer/Mux device, in other words, pin[7] to
the MSB through pin[0] to the LSB. For the Intel
example, pin[7] (the MSB on the Intel IXF6048) would be connected to
pin[0] (the MSB on the Intel
When Intel IXF6048 is configured as a single STS-12/STM-4/STS-3
(non-concatenated or concatenated) transceiver, TPDO_1[7:0],
TPDO_2[7:0], and TPDO_3[7:0] are tristated.
TPDO_i[7:0] (i = 0, 1, 2, 3) is updated on the rising edge of TPCO_i.
Transmit Parallel Clock Input TTL. TPCI_i (i = 0, 1, 2, 3) provides
timing for receive channel #i operation.
TPCI_i is a 77.76 MHz (622.08 Mbit/s), a 19.44 MHz (155.52 Mbit/s), or
a 6.48 MHz (51.84 Mbit/s) 50% duty cycle clock, providing timing for the
receive operation on channel #i (i = 0, 1, 2, 3).
When Intel IXF6048 is configured as a single STS-12/STM-4/STS-3
(non-concatenated or concatenated) transceiver, TPCI_1, TPCI_2, and
TPCI_3 are unused inputs.
®
GD16591A).
Description
®
GD16591A, for
Datasheet