RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 32

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
32
Table 4.
Pin Description (Sheet 18 of 66)
RSOH_0
RSOH_1
RSOH_2
RSOH_3
RSOHFR
RSOHCK
RSAL
RSALFR
RSALCK
TSOH_0
TSOH_1
TSOH_2
TSOH_3
TSOHINS_0
TSOHINS_1
TSOHINS_2
TSOHINS_3
TSOHFR
NOTE: See notes 1, 2, and
Pin Name
OH, Alarm, DCC and Orderwire Insertion/Extraction Ports Single PHY Mode (OH Ports Logical
G31
H29
K26
K28
E28
E30
H27
Pin
J28
J29
W3
W2
W1
U6
Y2
V5
Y1
V4
Y3
Interface #1) (Single OC-48c, OC-48, OC-12, and OC-3 Modes)
LVTTL
Output
4 mA
LVTTL
Output
4 mA
LVTTL
Output
4 mA
LVTTL
Output
4 mA
LVTTL
Output
4 mA
LVTTL
Output
4 mA
LVTTL
Input
LVTTL
Input
LVTTL
Output
4 mA
Type
3
at the end of the table.
Receive SOH Extraction Bus. RSOH_i (i = 0, 1, 2, 3) outputs the SOH
bytes extracted from the Incoming SONET/SDH frames.
RSOH_i (i = 0, 1, 2, 3) is clocked out by RSOHCK.
Receive SOH Frame Pulse. RSOHFR is an 8-KHz pulse indicating the
start of the SOH (A1 MSB position) on RSOH_i (i = 0, 1, 2, 3).
RSOHFR is clocked out by RSOHCK.
Receive SOH Extraction Clock. RSOHCK is a 20.736 MHz (OC-48c/
OC-48), 5.184 MHz (OC-12), or 1.728 MHz (OC-3) timing reference
signal used to clock out the RSOH_i (i = 0, 1, 2, 3) data.
Receive Section Alarm Bus. RSAL outputs the receive side section
alarms, detected section errors, generated remote defects, receive
filtered K1 and K2 APS bytes, and the filtered S1 SSM.
RSAL is clocked out by RSALCK.
Receive Section Alarm Pulse. RSALFR is an 8-KHz pulse indicating
the position of the generated RDI bit at RSAL. The RSALFR pulse
repeats every 72 clock cycles of RMDC.
RSALFR is clocked out by RSALCK.
Receive Section Alarm Clock. RSALCK is a 576-KHz timing reference
signal used to clock out the RSAL and RSALFR outputs.
Transmit SOH Insertion Bus. TSOH_i (i = 0, 1, 2, 3) inputs the SOH
bytes to be inserted in the outgoing SONET/SDH frames.
TSOH_i (i = 0, 1, 2, 3) is clocked in by TSOHCK.
Transmit SOH Insertion Enable. TSOHINS_i (i = 0, 1, 2, 3) is the
active-high SOH insertion enable. TSOHINS_i (i = 0, 1, 2, 3) controls the
insertion of the bytes transported on TSOH_i in the outgoing SONET/
SDH frames. The byte transported in TSOH_i (i = 0, 1, 2, 3) is inserted in
the outgoing frame if TSOHINS_i is asserted during its most significant
bit.
TSOHINS_i (i = 0, 1, 2, 3) control pin may be disabled via
microprocessor configuration register T_SC_RSOH[15] (TSOHINS_Ena
= ‘0’ in register address (1cc)E1H).
TSOHINS_i (i = 0, 1, 2, 3) is clocked in by TSOHCK.
Transmit SOH Frame Pulse. TSOHFR is an 8-KHz pulse indicating the
start of the SOH (A1 MSB position) on TSOH_i (i = 0, 1, 2, 3).
TSOHFR is clocked out by RSOHCK.
• In OC-48c, OC-48, and OC-12 modes, RSOH_i (i = 0, 1, 2, 3)
• In OC-3 mode, RSOH_i (i = 0, 1, 2, 3) extracts the SOH bytes
• In OC-48c, OC-48 and OC-12 modes, TSOH_i (i = 0, 1, 2, 3) inserts
• In OC-3 mode, TSOH_i (i = 0, 1, 2) inserts the SOH bytes to be
extracts the SOH bytes received in columns #i + 1, #i + 5, #i + 9, etc.
received in columns #i + 1, #i + 4, #i + 7, etc. RSOH_3 is held in high
impedance.
the SOH bytes to be transmitted in columns #i + 1, #i + 5, #i + 9, etc.
transmitted in columns #i + 1, #i + 4, #i + 7, etc. TSOH_3 is an
unused input.
Description
Datasheet