RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 265

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

11.4.7
11.4.8
Datasheet
15:10
15:6
Bit
2:0
Bit
5
4
3
9
8
7
6
5
4
Unused
RsTimOnCRC7ErrDsb
RsTimOnUnstableEn
RcvJ0_StableCnfg
RcvJ0_Cnf[2:0]
Reserved
OofOvrFlw
B1OvrFlw
Unused
J0Unstable
J0MsMtch
J0Crc7Err
Name
J0_RSTC—J0 Received Trace Configuration ((1cc)87H)
IS_RG—Receive Regenerator Section Interrupt Register ((1cc)D0H)
Each of these bits can cause the chip interrupt pin to become active if enabled via the bits in the
Receive Interrupt Enable Register 1.
Name
This bit sets when the OOF_ECNT error counter rollover occurs. It clears
when this register (IS_RG) is read.
This bit sets when the B1_ERRCNT error counter rollover occurs. It
clears when this register (IS_RG) is read.
This bit sets when there is a change in the J0UnstableSt bit (register
S_RG[6]). It clears when this register (IS_RG) is read.
This bit sets when there is a change in the J0MsMtchSt bit (register
S_RG[5]). It clears when this register (IS_RG) is read.
This bit sets when there is a change in the J0Crc7ErrSt bit (register
S_RG[4]). It clears when this register (IS_RG) is read.
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
This bit configures the setting of the Rs-Tim alarm i.e.,
J0MsMtchSt, when the CRC-7 is wrong:
'1' = An active J0Crc7ErrSt alarm masks the J0MsMtchSt
alarm (Rs-Tim), if (RsTimOnUnstableEn is low) or
(RsTimOnUnstableEn is high and J0UnstableSt is low).
'0' = J0MsMtchSt (Rs-Tim) alarm and J0CRC7ErrSt alarm
are two independent processes.
This bit configures the setting of the Rs-Tim alarm i.e.,
J0MsMtchSt, when the trace is unstable:
'1' = An active J0UnstableSt alarm forces the J0MsMtchSt
alarm (Rs-Tim) active.
'0' = J0MsMtchSt (Rs-Tim) alarm and J0UnstableSt alarm
are two independent processes.
This bit configures the number of consecutive identical
received Section Traces needed for the J0UnstableSt
(register S_RG bit #6) alarm to be cleared and for the
received section trace to be declared stable and accepted:
'1' = 5 consecutive identical messages.
'0' = 3 consecutive identical messages.
Configure J0 Receive Trace Identifier format:
'111' = Trace Identifier is a framed 64-byte string with 2
special ASCII characters: linefeed and carriage return.
'110' = Trace Identifier is a 64-byte string, free format.
'10X' = Trace Identifier is a 16-byte string + CRC-7 (SDH).
'01X' = Ignore J0 trace (no trace).
'00X' = Trace Identifier is a 1-byte string. (SONET)
Description
Description
Type
R/W
R/W
R/W
R/W
Type
R
R
R
R
R
Default
Default
'010'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
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