RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 30

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
30
Table 4.
Pin Description (Sheet 16 of 66)
RSDI_0
RSDI_1
RSDI_2
RSDI_3
RSCI_0
RSCI_1
RSCI_2
RSCI_3
RSCO_0
RSCO_1
RSCO_2
RSCO_3
RLOCK_0
RLOCK_1
RLOCK_2
RLOCK_3
ROOF_0
ROOF_1
ROOF_2
ROOF_3
RFPI_0
RFPI_1
RFPI_2
RFPI_3
NOTE: See notes 1, 2, and
Pin Name
AG30
AG29
AG27
AA26
AC26
AE26
AB26
AC31
AC28
AE27
AH27
AE31
AH31
AA27
AE29
AB30
AE30
AD26
AF26
AJ28
AJ27
W26
Y26
Y27
Pin
Receive 51 Mbit/s TTL Quad Serial Line Side Interface
LVTTL
Input
LVTTL
Input
LVTTL
Output
12 mA
LVTTL
Input
LVTTL
Output
12 mA
LVTTL
Input
Type
3
at the end of the table.
Receive Serial Data Input TTL
The receive TTL quad serial line side interface provides connection to
serial 51.84 Mbit/s demultiplexers. The quad serial mode can be used
when Intel IXF6048 is configured as a Quad STS-1/STM-0 transceiver.
RSDI_i (i = 0, 1, 2, 3) carries the incoming 51 Mbit/s serial data stream
for channel #i.
RSDI_i (i = 0, 1, 2, 3) is sampled on the rising edge of RSCI_i.
Receive Serial Clock Input TTL. RSCI_i (i = 0, 1, 2, 3) provides timing
for receive channel #i operation.
RSCI_i is a 51.84 MHz 50% duty cycle clock, providing timing for the
receive operation on channel #i (i = 0, 1, 2, 3).
Receive Serial Clock Output TTL. RSCO_i (i = 0, 1, 2, 3) is a flow-
through or divided version of RSCI_i.
RcvCOCnf (register R_COCNF) configures the RSCO_i (i = 0, 1, 2, 3)
outputs as a 51.84 MHz/25.92 MHz/12.96 MHz/6.48 MHz, or 8-KHz
clock.
Receive Lock Detect TTL. RLOCK_i (i = 0, 1, 2, 3) is the active-high
Lock Detect input for channel #i. RLOCK_i indicates that the external
clock recovery PLL used by channel #i is locked.
In single 32-bit mode, RLOCK_1, RLOCK_2, and RLOCK_3 are unused
inputs.
RLOCK_i (i = 0, 1, 2, 3) are asynchronous inputs.
Receive Out of Frame TTL. ROOF_i (i = 0, 1, 2, 3) is high while receive
channel #i is “out of frame” and low while it is “in frame”.
In single 32-bit mode, ROOF_1, ROOF_2, and ROOF_3 are tristated.
ROOF_i is updated on the rising edge of RSCI_i (i = 0, 1, 2, 3).
Receive Frame Position Input TTL. RFPI_i (i = 0, 1, 2, 3) are active-
high frame position inputs providing connection to an external SONET/
SDH demultiplexer. RFPI_i (i = 0, 1, 2, 3) indicates the SONET/SDH
frame position on the RPDI_i[7:0] bus.
Select the byte position indicated by RFPI_i (i = 0, 1, 2, 3) by using
RcvFPICnf[7:0] (global register R_FPCNF). RFPI_i (i = 0, 1, 2, 3) should
be active-high for a single RPCI_i period.
Receive channel #i ignores pulses on RFPI_i while “in frame” (ROOF_i =
'0').
In single mode RFPI_1, RFPI_2, and RFPI_3 are unused inputs.
RFPI_i is sampled on the rising edge of RPCI_i (i = 0, 1, 2, 3).
When frame alignment is enabled (bit RcvFBaDsbl = ‘0’ in register
R_RSTC), RFPI_i have to be tied to GND.
Description
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