RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 160

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
5.1.1.1
160
Figure 31. Cell Delineation State Diagram
HEC Verification and HEC-Based Cell Filtering
Normally, while in the PRESYNC state, no ATM cells are accepted. However, configuration bit
RcvPRESYNCCnf (channel register R_ACPCNF) allows passing (writing into the receive FIFO)
the correct ATM cells received while in the PRESYNC state.
While in the SYNC state, two operational modes are possible: Correction mode (normal operation)
and Detection mode.
In the Correction mode, the incoming ATM cells are processed as follows:
Upon discovery of a single- or multiple-bit error, the operation enters the Detection mode. While in
the Detection mode, the operation returns to the Correction mode after detecting ‘N’ consecutive
cells having a correct HEC sequence. All cells with correct HEC are accepted. The value of ‘N’ can
be set to four different values (1, 2, 4, or 8) by configuring RcvCorrDetCnf[1:0] (channel register
R_ACPCNF). Configuration bit RcvSYNCCnf (channel register R_ACPCNF) disables the HEC-
based cell filtering performed while in the SYNC state. If RcvSYNCCnf is set to logic one, all the
ATM cells received while in the SYNC state are accepted, regardless of the errors detected in the
HEC field.
Seven (ALPHA) consecutive cells with incorrect HEC, forces transition into the OCD (out of cell
delineation) state (PRESYNCH or HUNT states). Seven (1 + DELTA) consecutive cells with
correct HEC, forces the chip to exit the OCD state by going into the SYNC state). If OCD persists
for ‘M’ ms, the RACP enters the LCD (loss of cell delineation) state. The RACP leaves the LCD
state when the cell delineation process enters and remains in the SYNC state for longer than ‘M’
— Incoming ATM cells with no HEC errors are accepted.
— Incoming ATM cells with single-bit error are corrected and accepted.
— Incoming ATM cells with multiple-bit errors are dropped.
ALPHA consecutive
(cell-by-cell check)
HUNT
incorrect HECs
(cell-by-cell check)
Incorrect HEC
SYNC
DELTA consecutive
(cell-by-cell check)
correct HECs
PRESYNC
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