RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 191

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

7.2.7
7.2.8
8.0
Datasheet
The first method (configuration bits XmtIPGRelEn, XmtIPGRelCnf, and XmtIPGRel[2:0] in
register T_IPGCTRL) transmits, after each HDLC frame, a number of Flag characters proportional
to the length of the transmitted frame. Added Control Escape characters due to the byte stuffing
process are counted as extra bytes already added to the user’s data and are subtracted from the
number of flags to be inserted. This method reduces the POS-packet transmission rate.
The second method (configuration bits XmtIPGAbsEn, XmtIPGAbsCnf, and XmtIPGAbs[7:0] in
register T_IPGCTRL) transmits, after each HDLC frame, a constant number of Flag characters.
This method allows programming a minimum separation between consecutive HDLC frames.
Both methods can be used at the same time to ensure a maximum transmission rate and a minimum
interpacket gap simultaneously.
SPE Scrambling
Intel IXF6048 performs self-synchronous scrambling of the outgoing HDLC frames (the outgoing
SPE bytes) using the polynomial X
have been mapped into SPE (after FCS checking, byte stuffing, etc.). The self-synchronous
scrambling can be disabled by setting XmtScrEn = '0' (register T_PHCCNF).
Performance Monitoring Counters
POS-UTOPIA Interface Functional Description
The Intel IXF6048 UTOPIA interface is configured in either ATM mode (ATM-UTOPIA
interface) or in POS mode (POS-UTOPIA), depending on the configuration of the channel being
accessed through the interface. The configuration of the interface is totally independent in both the
transmit and the receive directions. When a transmit (or receive) channel is configured in ATM
mode (RcvChMode[1:0] = '11' in register R_COCNF or XmtChMode[1:0] = '11' in register
T_COCNF), the transmit (or receive) UTOPIA interface operates in POS mode for this channel. It
is possible to have a mixed configuration of channels working in ATM mode and channels in POS
mode.
The POS-UTOPIA interface connects a Link Layer device to the Intel IXF6048 (a Physical Layer
device). The POS-UTOPIA interface is an extension of the ATM industry standard UTOPIA,
adapted to support the transfer of variable length packets.
•
•
•
•
The number of packets read from the transmit FIFO and transmitted into HDLC frames are
counted in a 27-bit counter (register T_FRMCNT). This counter only counts the non aborted
frames, i.e., the frames aborted by the user or unsuccessfully transmitted due to a FIFO
underflow error are not counted.
The number of bytes read from the transmit FIFO and transmitted into the generated HDLC
frames are counted in a 29-bit counter (register T_BYTECNT).
The number of HDLC frames that have been aborted by the user are counted in a 20-bit
counter (register T_AFCNT).
The number of HDLC frames that have been aborted by the HDLC controller due to a transmit
FIFO underflow are counted in a 16-bit counter (register T_PFUCNT).
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
43
+ 1. The scrambling is performed after the HDLC frames
191