RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 192

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
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The interface can operate using a port selection cycle (such as the ATM-UTOPIA interface) or
with no port selection cycle.
The interface can operate at up to 104 MHz in the single 32-bit, 16-bit, and 8-bit modes as well as
in the quad 8-bit mode. The interface can operate at up to 52 MHz in the single 64-bit mode and the
quad 16-bit mode.
The receive and transmit FIFO memories provide for the separation of the Physical Layer timing
and the Data Link Layer timing. The FIFOs are also necessary to handle the rate differences caused
by the insertion/removal of Control Escape characters:
The interface can be configured as a single interface or as four independent 8-bit interfaces by
setting RcvUMode[1:0] in register R_UICNF.
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When the POS-UTOPIA interface is configured to use a port selection cycle, the interface
operates in the same way as the ATM-UTOPIA interface: two processes (data transfer and
FIFO status polling) are performed simultaneously.
When the POS-UTOPIA interface is configured to not use a port selection cycle, the interface
operates as a simple memory mapped device.
When Intel IXF6048 is configured as a Single concatenated transceiver (a single Physical port
transporting a single HDLC frame stream), only one channel is enabled and connected to the
interface using a 2 or 16-Kbyte FIFO memory (selectable).
When Intel IXF6048 is configured as a Quad transceiver (four Physical ports) or as a Single
non-concatenated transceiver (a single Physical port transporting four independent HDLC
frame streams), channel #0 is connected to the interface using a 16-Kbyte FIFO memory while
channels #1, #2, and #3 use a 2-Kbyte FIFO memory. Optionally, the size of the FIFO for
channel #0 can be limited to 2-Kbytes by setting XmtSmallMem (transmission) in register
T_UICNF and RcvSmallMem (reception) in register R_UICNF.
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