RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 53

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Datasheet
Table 4.
Pin Description (Sheet 39 of 66)
TXENB
TXADDR[0]
TXADDR[1]
TXADDR[2]
TXADDR[3]
TXADDR[4]
TXSOF
TXEOF
TXPRTY
NOTE: See notes 1, 2, and
Pin Name
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
D10
D11
Pin
M6
D9
A8
C9
A9
H1
J2
LVTTL
Input
LVTTL
Input
LVTTL
Input
LVTTL
Input
LVTTL
Input
Type
3
at the end of the table.
Transmit Write Enable. TXENB (active-low) controls write access to the
transmit interface. TXENB can be used in two different ways:
Normal mode (with port selection phase)
This is the default mode of configuration (XmtSelMode = '0', register
T_UICNF), compatible with the UTOPIA Level 3 and Level 2
specifications.
Memory mapped device mode (with no port selection phase)
This configuration (XmtSelMode = '1', register T_UICNF) simplifies the
standard UTOPIA interface by eliminating the port selection phase. Port
selection is performed in a clock cycle basis:
TXENB is sampled on the rising edge of TXCLK.
Transmit Address Bus. TXADDR[4:0] are used to perform two different
processes:
The most significant three bits of the address (TXADDR[4:2]) are
compared with the base-address programmed value (UAddrBase[2:0],
global register GOCNF) to determine if the device has been selected.
The least significant two bits of the address (TXADDR[1:0]) are hard-
wired to select a specific channel ('00' = channel 0, '01' = channel 1, '10'
= channel 2, '11' = channel 3).
The address value 1FH is the null physical address and cannot be
assigned to any PHY port.
TXADDR[4:0] are sampled on the rising edge of TXCLK.
Transmit Start-of-Frame. TXSOF (active-high) marks the first word of a
frame (cell or packet) in TXDATA. In transmission, all the frames (cells or
packets) are input in TXDATA with the first frame byte located in the
most significant byte position.
TXSOF is sampled on the rising edge of TXCLK.
Transmit End-of-frame. TXEOF (active-high) marks the last word of a
frame (cell or packet) in TXDATA. TXEOF is used only in POS mode; in
ATM mode, TXEOF is an unused input.
TXEOF is sampled on the rising edge of TXCLK.
Transmit Data Parity. TXPRTY indicates the parity of TXDATA. Odd or
even parity is selectable (see XmtPrtyCng in register T_UICHCNF).
TXPRTY is sampled on the rising edge of TXCLK.
• Port selection phase: when TXENB is deasserted, no read
• Data transfer phase: when TXENB is asserted, the FIFO selected
• When TXENB is deasserted, nothing happens.
• When TXENB is asserted, the FIFO indicated by TXADDR[4:0] (on a
• To select a particular FIFO for a data transfer.
• To poll the status of a particular FIFO (independently of TXENB).
operations are performed and TXADDR[4:0] are sampled into
latches to select (or reselect) a port for a data transfer.
during the port selection phase is written.
clock cycle basis) is written.
Description
53