RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 162

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
5.1.1.6
5.2
5.2.1
5.2.2
162
Receive FIFO Control
The receive FIFO memory—one 32/256-cell deep and three 32-cell deep FIFOs in a four-channel
application or a single 32/256-cell deep FIFO in a one-channel application—stores the received
non-dropped ATM cells, thereby providing for the separation of the TCS timing from the ATM
layer timing. The channel 0 receive FIFO is configurable to either 32 or 256 cells deep by the user.
It is then read by the receive ATM-UTOPIA interface. The receive FIFO is controlled on a cell
basis. If the FIFO is full of cells and there is a cell to be stored—the ATM layer has failed to keep
up with the incoming ATM cell traffic—the cell is discarded and the problem is indicated via a
maskable software interrupt.
Transmit ATM Cell Processing
When Intel IXF6048 is configured as a Quad transceiver (STS-1/STS-3c/STM-1/STS-12c/STM-
4c) or as a Single transceiver (OC-48/STM-16/STM-4 (non-concatenated)), each of the four
transmit ATM cell processors (TACP) reads the ATM Layer cells from a FIFO memory and maps
them as a continuous ATM-cell stream on the corresponding SPE. The FIFO memory is 32/256-
cell deep in the first channel and 32-cell deep in the other three channels.
When Intel IXF6048 is configured as a Single transceiver (OC-48c/STM-12c (concatenated)), only
one TACP is active. It reads the ATM Layer cells from a 32/256-cell deep FIFO memory and maps
them as a continuous ATM-cell stream on the outgoing SPE. The channel 0 transmit FIFO is
configurable to either 32 or 256 cells deep by the user.
Transmit FIFO Control
The transmit FIFO memory—one 32/256-cell deep and three 32-cell deep FIFOs in a 4-channel
application or a single 32/256-cell deep FIFO in a one-channel application—stores the ATM Layer
cells to be transmitted, thereby providing for the separation of the TCS timing from the ATM layer
timing It is then read by the corresponding TACP. The transmit FIFO is controlled on a cell basis.
Prior to mapping a new cell in the outgoing SONET/SDH frame, the TACP checks the transmit
FIFO status. If the FIFO contains an entire ATM cell, the TACP reads the cell and begins its
transmission. Otherwise, an idle cell is automatically generated (cell rate decoupling process).
Idle/Unassigned Cell Insertion
Channel register T_ICELLP is used to configure the values of the CFG, PTI, and CLP fields, as
well as the payload pattern for the cells generated and inserted in the cell rate decoupling process.
The inserted cells are generated with VPI and VCI containing the all '0's pattern.
— The number cells containing an uncorrectable error in the header are counted in a 16-bit
— The number of accepted cells that have been lost, due to a FIFO overflow, are counted in
counter (channel register R_UHECNT).
a 16-bit counter (channel register R_CFOCNT).
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