RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 43

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Datasheet
Table 4.
Pin Description (Sheet 29 of 66)
RXDATA[0]
RXDATA[1]
RXDATA[2]
RXDATA[3]
RXDATA[4]
RXDATA[5]
RXDATA[6]
RXDATA[7]
RXDATA[8]
RXDATA[9]
RXDATA[10]
RXDATA[11]
RXDATA[12]
RXDATA[13]
RXDATA[14]
RXDATA[15]
RXDATA[16]
RXDATA[17]
RXDATA[18]
RXDATA[19]
RXDATA[20]
RXDATA[21]
RXDATA[22]
RXDATA[23]
RXDATA[24]
RXDATA[25]
RXDATA[26]
RXDATA[27]
RXDATA[28]
RXDATA[29]
RXDATA[30]
RXDATA[31]
NOTE: See notes 1, 2, and
Pin Name
Receive Single MPHY ATM/POS-UTOPIA Interface (Level 3 and Level 2 Modes)
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
D13
B13
A12
A14
A13
D14
F14
B14
D16
B18
B17
D17
A18
A19
F16
A20
F20
B23
B24
C22
E21
D21
C23
D22
A27
C25
B26
E23
C26
D25
B27
F23
Pin
LVTTL
Output
12 mA
Type
3
at the end of the table.
Receive UTOPIA Data Bus
RXDATA[63:0] carries the frame (cell or packet) word that is read from
the receive FIFO memories. RXDATA[63:0] transports the cell/packet
data in 64-bit, 32-bit, 16-bit, or 8-bit format (RcvUWidth, register
R_UICNF).
When configured in 8-bit mode, RXDATA[31:8] are held in high
impedance and RXDATA[7:0] contains valid data.
RXDATA is driven when the receive interface has been selected for a
data transfer or RcvMphyDevCnf = '0' (register R_UICNF).
RXDATA is tristated when the receive interface has not been selected
for a data transfer and RcvMphyDevCnf = '1' (register R_UICNF).
NOTE: Depending on the configuration of RcvDRCnf (register
NOTE: To operate in Level 3 mode (Intel IXF6048 does not share the
NOTE: If the receive interface operates in Level 2 or Level 1 modes and
RXDATA[63:0] are updated on the rising edge of RXCLK.
• When configured in 64-bit mode, RXDATA[63:56] transports the
• When configured in 32-bit mode, RXDATA[31:24] transports the
• When configured in 16-bit mode, RXDATA[31:16] are held in high
most significant byte.
most significant byte.
impedance and RXDATA[15:0] contains valid data. RXDATA[15:8]
transports the most significant byte.
R_UICHCNF), a data transfer happens one (UTOPIA Level 2) or
two (UTOPIA Level 3) clock cycles after the assertion of
RXENB.
interface with other PHYs) RcvMphyDevCnf must be set to logic
zero.
Intel IXF6048 does not share the interface with other PHYs,
then RcvMphyDevCnf should be set to logic zero.
Description
43