RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 252

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
252
Bit
2:1
4
3
0
XmtMPhyDevCnf
XmtUQuad
XmtUWidth[1:0]
XmtSelMode
Name
XmtMPhyDevCnf configures the transmit interface as follows:
'1' = The transmit output TXPFA is only driven when TXADDR
matches the programmed device address (Level 2 mode). This
setting must be used when Intel IXF6048 shares the transmit
interface with other PHY devices.
'0' = The transmit output TXPFA is always driven. This setting can
be used when Intel IXF6048 is the only PHY device in the transmit
interface.
XmtUQuad sets the transmit UTOPIA interface.
'0' = Single transmit UTOPIA interface.
'1' = Quad transmit UTOPIA interface.
XmtUWidth[1:0] sets the width of the transmit UTOPIA data bus
(TXDATA):
'00' = 8-bit data interface
'01' = 16-bit data interface
'10' = 32-bit data interface
'11' = 64-bit data interface
NOTE: when the transmit UTOPIA interface is configured in Quad
XmtSelMode configures the transmit POS-UTOPIA interface port
selection mode.
'0' = The transmit POS-UTOPIA interface operates similar to the
ATM-UTOPIA interface, with two independent processes running
in parallel: the data transfer and the port selection. TXADDR[4:0]
are used to select a port when TXENB changes from '1' to '0' and
to poll the status of the FIFOs (using the output TXPFA). Once the
port is selected (TXENB = '0'), TXADDR[4:0] can take any value
(FIFO status polling using TXPFA).
'1' = The POS-UTOPIA interface is controlled as a memory
mapped device. There is no selection cycle or FIFO status polling,
just port addressing. The TXPFA output is not used and the status
of each FIFO is indicated using the direct outputs TXFA_0,
TXFA_1, TXFA_2, and TXFA_3. Nothing happens when TXENB =
'1'. If TXENB = '0', the value transferred in TXDATA is written in the
FIFO indicated by TXADDR[4:0].
mode (XmtUQuad set to logic one), configuration values
'10' (32-bit) and '11' (64-bit) are invalid.
Description
Type
R/W
R/W
R/W
R/W
Datasheet
Default
'10'
'0'
'0'
'0'