RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 295
RCLXT16706FE
Manufacturer Part Number
RCLXT16706FE
Description
Manufacturer
Intel
Datasheet
1.RCLXT16706FE.pdf
(352 pages)
Specifications of RCLXT16706FE
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
2.97V
Operating Supply Voltage (max)
3.63V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Not Compliant
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11.8.4
11.8.5
Datasheet
13:8
15:8
Bit
7:0
Bit
7:0
15
14
XmtJ0StrgWrite
XmtJ0StrgRead
XmtJ0StrgAddr[5:0]
XmtJ0StrgData[7:0]
XmtK2[7:0]
XmtK1[7:0]
T_J0_STRA—J0 Transmit String Data Access Register ((1cc)E4H)
This register allows the configuration of the J0 string to be transmitted in the outgoing SOH. See
the R_J0_ESTRA register description for the configuration procedure.
MP_TK2K1—Microprocessor Provided Transmit K1 and K2 Bytes
Register ((1cc)E5H)
Name
Name
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
Bits [15:8] correspond to XmtK2[7:0], respectively.
Bits [7:0] correspond to XmtK1[7:0], respectively.
XmtJ0StrgWrite is the Write Command operational bit for the
transmit J0 string internal RAM:
When the microprocessor writes to this bit:
'0' = No consequent action.
'1' = Write XmtJ0StrgData[7:0] data byte into the expected
string RAM at XmtJ0StrgAddr[5:0] address location (string
pointer). XmtJ0StrgWrite bit clears automatically when this
operation is completed.
When the microprocessor reads this bit:
'0' = The internal expected string RAM is ready for a new write
operation. The previous write operation, if any, has been
completed.
'1' = A write operation is pending; the internal expected string
RAM is busy and no new read or write operation to this RAM is
allowed.
XmtJ0StrgRead is the Read Command operational bit for the
transmit J0 string internal RAM:
When the microprocessor writes to this bit:
'0' = No consequent action.
'1' = Download XmtJ0StrgData[7:0] data byte from the
XmtJ0StrgAddr[5:0] address location (string pointer) of the
expected string RAM into an internal register. XmtJ0StrgRead
bit clears automatically when this operation is completed. The
microprocessor accesses the downloaded value by performing
a read at address (1cc)E4H (XmtJ0StrgData[7:0] value) and
reading XmtJ0StrgRead as '0'.
When the microprocessor reads this bit:
'0' = The internal expected string RAM is ready for a new read
operation. The previous read operation, if any, has been
completed.
'1' = A read operation is pending; the internal expected string
RAM is busy and no new read/write operation to this RAM is
allowed.
Bits [5:0] represents the string pointer value (RAM address)
Bits [7:0] correspond to Data bits [7:0], respectively.
Description
Description
R/W
R/W
R/W
R/W
Type
Type
R/W
R/W
'0'
'0'
000000
00H
Default
Default
00H
00H
295
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