RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 348

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
13.1.1
13.1.2
348
Instruction Register and Definitions
The Intel IXF6048 supports the following instructions identified by IEEE 1149.1: EXTEST,
SAMPLE/PRELOAD, BYPASS, and IDCODE:
EXTEST (‘b00): Allows circuitry external to the package (typically the board interconnect) to be
tested. While the instruction is active, the boundary scan register is connected between JTDI and
JTDO. Signals present on input pins are loaded into the BSR inputs cells on the rising edge of
JTCK during CAPTURE-DR state of the TAP controller. BSR input cell contents are shifted one
bit location on each rising edge of JTCK during the TAP’s SHIFT-DR state. BSR output cell
contents appear at output pins on the falling edge of JTCK during the TAP’s UPDATE-IR state.
SAMPLE/PRELOAD (‘b01): This instruction creates a snapshot of the normal operation of the
Intel IXF6048. The boundary scan register is connected between JTDI and JTDO for any data
shifts while this instruction is active. All BSR cells capture data present at their inputs on the rising
edge of JTCK during the CAPTURE-DR state. No action is taken during the UPDATE-DR state.
BYPASS (‘b11): BYPASS allows a device to be removed from the scan chain by inserting a one-
bit shift register stage between JTDI and JTDO during data shifts. When the instruction is active,
the test logic has no impact upon the system logic performing its function. When selected, the shift-
register is set to a logic zero on the rising edge of the JTCK during the CAPTURE-DR state.
IDCODE (‘b10): IDCODE allows the reading of component types via the scan chain. During this
instruction, the 32-bit Device Identification Register (ID-Register) is placed between JTDI and
JTDO. The ID Register captures a fixed value on the rising edge of JTCK during the CAPTURE-
DR state. The Device Identification Register contains the following information: Manufacturer ID:
‘d126; Design Part Number: ‘d 6048; Design Version Number: ‘d1.
The EXTEST, SAMPLE/PRELOAD, BYPASS, and IDCODE instructions are shifted into the
instruction register during the SHIFT-IR state and become active upon exiting the UPDATE-IR
state.
Boundary Scan Register
The Boundary Scan Register is a 614-bit shift register composed of 2 types of shift-register cells, as
depicted in
Control signals. More specific information regarding the Boundary Scan Register and individual
Boundary Scan Cells may be obtained from the Boundary Scan Description Language (BSDL) file,
which is available upon request.
Figure
100. Type 1 is specifically for clock inputs; Type 2 is used for all other I/O and
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