RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 37

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Datasheet
Table 4.
Pin Description (Sheet 23 of 66)
RSOH_0
RSOH_1
RSOH_2
RSOH_3
RSOHFR_0
RSOHFR_1
RSOHFR_2
RSOHFR_3
RSOHCK_0
RSOHCK_1
RSOHCK_2
RSOHCK_3
RSAL_0
RSAL_1
RSAL_2
RSAL_3
RSALFR_0
RSALFR_1
RSALFR_2
RSALFR_3
RSALCK_0
RSALCK_1
RSALCK_2
RSALCK_3
TSOH_0
TSOH_1
TSOH_2
TSOH_3
TSOHINS_0
TSOHINS_1
TSOHINS_2
TSOHINS_3
TSOHFR_0
TSOHFR_1
TSOHFR_2
TSOHFR_3
NOTE: See notes 1, 2, and
OH and Alarm Insertion/Extraction Ports Quad PHY Mode (OH Ports Logical Interface #2) (Quad OC-
Pin Name
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
G31
G27
G28
AA1
H29
K26
H30
H31
K27
K28
E28
F27
E29
E30
H26
E31
F28
H27
F29
J28
J29
L26
J30
J31
J26
Pin
W3
W2
W1
W4
Y2
V5
Y1
U6
V4
Y3
V6
LVTTL
Output
4 mA
LVTTL
Output
4 mA
LVTTL
Output
4 mA
LVTTL
Output
4 mA
LVTTL
Output
4 mA
LVTTL
Output
4 mA
LVTTL
Input
LVTTL
Input
LVTTL
Output
4 mA
Type
3
at the end of the table.
Receive SOH Extraction Bus. RSOH_i (i = 0, 1, 2, 3) outputs the SOH
bytes extracted from the incoming SONET/SDH frames on channel #i.
RSOH_i (i = 0, 1, 2, 3) is clocked out by RSOHCK_i.
Receive SOH Extraction Frame Pulse. RSOHFR_i (i = 0, 1, 2, 3) is an
8-KHz pulse indicating the start of the SOH (A1 MSB position) on
RSOH_i.
RSOHFR_i (i = 0, 1, 2, 3) is clocked out by RSOHCK_i.
Receive SOH Extraction Clock. RSOHCK_i (i = 0, 1, 2, 3) is a 20.736
MHz (Quad OC-12c), 5.184 MHz (Quad OC-3c), or 1.728 MHz (Quad
OC-1) timing reference signal used to clock out the RSOH_i data on
channel #i.
Receive Section Alarm Bus. RSAL_i (i = 0, 1, 2, 3) outputs the receive
side section alarms, detected section errors, generated remote defects,
receive filtered K1 and K2 APS bytes, and the filtered S1 SSM on
channel #i.
RSAL_i (i = 0, 1, 2, 3) is clocked out by RSALCK_i.
Receive Section Alarm Pulse. RSALFR_i (i = 0, 1, 2, 3) is an 8-KHz
pulse indicating the position of the generated RDI bit at RSAL_i. The
RSALFR_i pulse (i = 0, 1, 2, 3) is repeated every 72 clock cycles of
RSALCK_i.
RSALFR_i (i = 0, 1, 2, 3) is clocked out by RSALCK_i.
Receive Section Alarm Clock. RSALCK_i (i = 0, 1, 2, 3) is a 576-KHz
timing reference signal used to clock out the RSAL_i and RSALFR_i
outputs on channel #i.
Transmit SOH Insertion Bus. TSOH_i (i = 0, 1, 2, 3) inputs the SOH
bytes to be inserted in the outgoing SONET/SDH frames on channel #i.
TSOH_i (i = 0, 1, 2, 3) is clocked in by TSOHCK.
Transmit SOH Insertion Enable. TSOHINS_i (i = 0, 1, 2, 3) is the
active-high SOH insertion enable. TSOHINS_i (i = 0, 1, 2, 3) controls the
insertion of the bytes transported on TSOH_i in the SONET/SDH frames
generated by channel #i. The byte transported in TSOH_i (i = 0, 1, 2, 3)
is inserted in the outgoing frame if TSOHINS_i is asserted during its
most significant bit.
TSOHINS_i (i = 0, 1, 2, 3) control pin may be disabled via
microprocessor configuration register T_SC_RSOH[15] (TSOHINS_Ena
= ‘0’ in register address (1cc)E1H).
TSOHINS_i (i = 0, 1, 2, 3) is clocked in by TSOHCK_i.
Transmit SOH Insertion Frame Pulse. TSOHFR_i (i = 0, 1, 2, 3) is an
8-KHz pulse indicating the start of the SOH (A1 MSB position) on
TSOH_i.
TSOHFR_i (i = 0, 1, 2, 3) is clocked out by TSOHCK_i.
12c, OC-3c, and OC-1 Modes)
Description
37