RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 45

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Datasheet
Table 4.
Pin Description (Sheet 31 of 66)
RXENB
RXADDR[0]
RXADDR[1]
RXADDR[2]
RXADDR[3]
RXADDR[4]
RXSOF
RXEOF
NOTE: See notes 1, 2, and
Pin Name
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
E19
C18
B19
C19
B20
A21
C12
B11
Pin
LVTTL
Input
LVTTL
Input
LVTTL
Output
12 mA
LVTTL
Output
12 mA
Type
3
at the end of the table.
Receive Read Enable. RXENB is the active-low receive enable and
controls read access from the Intel IXF6048 receive interface. RXENB
can be used in two different ways:
Normal Mode (with port selection phase)
This is the default configuration (RcvSelMode = '0', register R_UICNF)
compatible with the UTOPIA Level 3 and Level 2 specifications.
Memory Mapped Device Mode (with no port selection phase)
This configuration (RcvSelMode = '1', register R_UICNF) simplifies the
standard UTOPIA interface by eliminating the port selection phase. Port
selection is performed on a clock cycle basis:
RXENB is sampled on the rising edge of RXCLK.
Receive Address Bus. RXADDR[4:0] are used to perform two different
processes:
The most significant three bits of the address (RXADDR[4:2]) are
compared with the base-address programmed value (UAddrBase[2:0],
global register GOCNF) to determine if the device has been selected.
The least significant two bits of the address (RXADDR[1:0]) are hard-
wired to select a specific channel ('00' = channel 0, '01' = channel 1, '10'
= channel 2, '11' = channel 3).
The address value 1FH is the null physical address and cannot be
assigned to any PHY port.
RXADDR[4:0] are sampled on the rising edge of RXCLK.
Receive Start-of-Frame. RXSOF (active-high) marks the first word of a
frame (cell or packet) in RXDATA. In reception, all the cells/packets are
transferred in RXDATA with the first byte of the frame located in the most
significant byte position (see the RXDATA description).
RXSOF is driven or tristated following the same rules as RXDATA.
RXSOF is updated on the rising edge of RXCLK.
Receive End-of-Frame. RXEOF (active-high) marks the last word of a
frame (cell or packet) in RXDATA. RXEOF is used only in POS mode; in
ATM mode, this output is held in high impedance (see RcvTestOen in
register R_UICNF).
RXEOF is driven or tristated following the same rules as RXDATA.
RXEOF is updated on the rising edge of RXCLK.
• Port selection phase: when RXENB is deasserted, no read
• Data transfer phase: when RXENB is asserted, the FIFO selected
• When RXENB is deasserted, nothing happens.
• When RXENB is asserted, the FIFO indicated by RXADDR[4:0]
• To select a particular FIFO for a data transfer
• To poll the status of a particular FIFO (independently of RXENB)
operations are performed and RXADDR[4:0] are sampled into
latches to select (or reselect) a port for a data transfer.
during the port selection phase is read and the data is output in
RXDATA, RXPRTY, RXSOF, RXEOF, RXERR, and RXVAL after
one or two clock cycles (see RcvDRCnf bit in register R_UICHCNF).
(during the same clock cycle) is read and the data is output in
RXDATA, RXPRTY, RXSOF, RXEOF, RXERR, and RXVAL after
one or two clock cycles (see RcvDRCnf bit in register R_UICNF).
Description
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