RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 153
RCLXT16706FE
Manufacturer Part Number
RCLXT16706FE
Description
Manufacturer
Intel
Datasheet
1.RCLXT16706FE.pdf
(352 pages)
Specifications of RCLXT16706FE
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
2.97V
Operating Supply Voltage (max)
3.63V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Not Compliant
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4.5.5
4.5.5.1
4.5.5.2
Receive Regenerator Section OverHead Serial DCC Timing
RRDC
RRD
Data Communication channel
Datasheet
Transmit Regenerator Section OverHead Serial DCC Timing
TRDC
TRD
Data Communication channel
Figure 21. Transmit D1 to D3 Timing
Figure 22. Receive D1 to D3 Timing
Input D1 to D3
Input D1 to D3
Output clock
( 192 KHz )
Output clock
( 192 KHz )
Dedicated Serial Accesses to DCC and Orderwires
D1 to D3 Data Communication Channel
For each regenerator section processed in the Intel IXF6048 (up to four), the interface is described
below.
4.5.5.1.1 Transmit Side Access (i = 0, 1, 2, 3)
4.5.5.1.2 Receive Side Access (i = 0, 1, 2, 3)
D4 to D12 Data Communication Channel
For each multiplex section processed in the Intel IXF6048 (up to four), the interface is described
below.
Data bit
— Data input is TRD[i] (192-Kbit/s serial access).
— Clock reference is TRDC[i]. This 192-KHz signal is a square wave, synchronous with the
— TOWBYC[i] can be used to identify the byte position, relative to the transmit frame.
— Data Output is RRD[i].
— Clock reference is RRDC[i]. This 192-KHz signal is a square wave, synchronous with the
— ROWBYC[i] can be used to identify the byte position, relative to the receive frame.
transmit clock.
receive clock.
Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit
Data bit
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit Data bit Data bit
Data bit Data bit Data bit
Data bit
Data bit Data bit
Data bit
Data bit
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