RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 161

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

5.1.1.2
5.1.1.3
5.1.1.4
5.1.1.5
Datasheet
Figure 32. HEC Verification State Diagram (While in SYNC State)
ms. Parameter ‘M’ defaults to 1 ms for OC-48c but it can be changed by using channel register
R_LCDFLTR. Software status bits (channel register R_ATMINT) and maskable interrupt bits
(channel register R_ATMINT) indicate the current OCD and LCD states.
Idle/Unassigned Cell Filtering
A programmable filter, consisting of 8-bit patterns and an 8-bit mask (channel register
R_IUCFLTR), allows identification and dropping of the idle/unassigned cells by comparing the
incoming GFC, PTI, and CLP bits with the programmed mask. A cell is dropped if the cell header
matches this mask while both VPI and VCI fields contain the all '0's pattern. This function can
optionally be disabled.
Cell Payload Descrambling
The 48-byte cell payload is descrambled using a self-synchronizing descrambler with the
polynomial X
GFC Processing
Intel IXF6048 allows the software to monitor the incoming Generic Flow Control (GFC) bits to
determine the remote device configuration: controller device, controlled device, or no GFC
functions implemented. When the GFC is enabled in the system, Intel IXF6048 can be configured
as a controlled or a controlling device. When configured as a controlled device, every time a cell is
received with the “halt bit” GFC[3] set, an idle/unassigned cell is inserted in the transmit stream.
Performance Monitoring Counters
— The number of cells that have been sent to the receive FIFO (cells passing the configured
— The number of cells matching the Idle/Unassigned programmable filter (channel register
— The number cells containing a correctable error in the header are counted in a 16-bit
cell filter) are counted in a 24-bit counter (channel register R_ACELLCNT).
R_IUCFLTR) are counted in an 24-bit counter (channel register R_ICELLCNT).
counter (channel register R_CHECNT).
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
(from PRESYNC state)
43
DELTA consecutive
CORRECTION
+ 1. This function can optionally be disabled.
correct HECs
detected
No error
MODE
(pass
cell)
(correct error and
No error detected in
N consecutive cells
Single-bit error
Multi-bit error
(pass Nth cell)
(drop cell)
pass cell)
ALPHA consecutive
(to HUNT state)
incorrect HECs
DETECTION
(drop cell)
detected
MODE
Error
consecutive correct
No error detected,
but is not the Nth
cell (pass cell)
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