RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 118

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
4.4.1.4
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4.4.1.3.6 National Used/Z0 Bytes, Media Dependent, and Undefined Bytes
These bytes are only relevant in OC-3/12/48 mode and can only be accessed via the serial RSOH
output.
4.4.1.3.7 Receive Regenerator Section AIS (RstAIS)
The AIS generated after the Regenerator Section is labeled RstAis. It can be inserted on the
following conditions:
These conditions can be individually enabled or disabled (see register R_RSTC). A test register
that can force an RstAis for test purposes is also available. RstAis insertion is indicated in global
register S_AIS for each of the 4 channel.
Multiplexer Section Receiver
The Multiplexer Section receiver handles the MSOH overhead bytes required for ATM/POS
Physical Layer operation.
4.4.1.4.1 B2 Error Bytes
These bytes are used for Multiplexer Section error monitoring. The B2 errors are counted either as
block error in registers B2_BLKCNT (17-bit) or as bit errors in registers B2_BIPCNT (22-bit
counter). In STM-1 mode, a block is equivalent to an entire frame. In STM-4 and STM-16 modes,
a block has two definitions (see register configuration R_MST_C):
An Excessive Error Defect (EED) indication (see register IS_MUX) is generated by integrating
the B2 errors in a sliding window. Integration is also used when clearing the EED indication. Six
registers allow the configuration of EED indication thresholds, hysteresis, and probability of
detection. They are WINSZ_SB2, CWIN_SB2, E#_EXCWIN_SB2, WINSZ_CB2, CWIN_CB2,
and E#_NEXCWIN_CB2 registers. These six registers allow configuring the EED thresholds
(BER setting and clearing thresholds are fully independent) from a Bit Error Rate of 10–3 to a bit
error rate of 10–8 or lower, even in the case of a non-Gaussian statistical distribution of errors. An
active EED indication can be configured to insert an AIS signal, to generate Signal Fault defect,
and/or to generate an RDI defect (see register R_MST_C, bit #7 and #2).
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Internally processed Loss Of Signal (LOS)
External Receive Loss Of Clock Synchronization alarm input (RLOCK)
Loss Of Frame (LOF)
Trace Identification Mismatch (J0MsMtch)
The entire STM-4 or STM-16 frame.
An STM-1 equivalent frame, which is four blocks in STM-4 and sixteen blocks in STM-16.
of the RSOH
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