RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 141

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

4.5.2.2
Datasheet
Transmit higher order Path OverHead Serial Bus Timing
TPOHFR[i]
TPOH[i]
TPOHCK[i]
TPOHFR[i]
TPOHINS[i]
TPOH[i]
Output frame pulse
Figure 15. Transmit HPOH Serial Bus Timing
Input data
Input data
Output frame pulse
Output clock
(576 KHz)
Input data insertion control
For each interface, the reference clock is supplied by TPOHCK[i] at 576-KHz. TPOHCK[i] is
synchronous with the transmit Higher Order Payload rate.
Frame pulse output TPOHFR[i] indicates the expected presence of J1 MSB at TPOH input. It is
repeated every 125 µs.
The Intel IXF6048 latches the data on the TPOH pin, synchronized with the timing signals. If the
TPOHINS input insert control pin is high at any bit location of a specific POH byte in the TSOH
input bus, this bit value is inserted into the transmit POH byte and output from the Intel IXF6048.
If the TPOHINS input control pin is low at the bit location of a specific POH byte in the TPOH
input bus, the transmit bit value of this POH byte comes from the source specified by configuration
register T_HPT_C (default value, internal hardware process, microprocessor, dedicated serial
accesses, or received byte).
When the TPOHINS insert control pin is enabled via the microprocessor interface (TPOHINS_Ena
= ‘1’ in register T_HPT_C[15]), it takes precedence on any software configuration regarding the
POH bytes transmit source; TPOHINS control logic is based on a bit-per-bit insertion from the
TPOH serial input. If the TPOHINS insert control pin is disabled via the microprocessor interface
(TPOHINS_Ena = ‘0’ in register T_HPT_C[15]), then the transmit POH bytes cannot be sourced
from the TPOH serial interface.
Receive Side: RPOH Serial Bus
The Receive side POH interface provides all the signals necessary to serially collect the POH
receive bytes via the serial codirectional interfaces (up to four) described below.
— Frame pulse RPOHFR[i] indicates the presence of J1 MSB at RPOH output. It is repeated
— The RPOHCK[i] reference clock at 576-KHz is used for clocking the RPOH[i] output.
J1 byte
every 125 µs.
J1 MSB
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
B3 byte
J1 bit 6
Every Frame
J1 bit 5
C2 byte
1 frame: 125 µs <=> 72 x TPOHCK clock cycles
J1 bit 4
J1 bit 3
G1 byte
J1 bit 2
F2 byte
J1 bit 1
H4 byte
J1 LSB
B3 MSB
F3/Z3 byte
8 clock
cycles
B3 bit 6
K3/Z4 byte
B3 bit 5
K3 bit 5
N1/Z5 byte
J1 byte
141