R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 117
R5F61525
Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5F61525.pdf
(846 pages)
- Current page: 117 of 846
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4.5
4.5.1
Instruction fetch, stack operation, data read/write, and single-address transfer shown in table 4.5
may cause an address error.
Table 4.5
Type
Instruction fetch CPU
Stack operation CPU
Data read/write CPU
Data read/write DMAC
Address Error
Address Error Source
Bus Cycle
Bus Cycle and Address Error
Bus Master
Description
Fetches instructions from even addresses
Fetches instructions from odd addresses
Fetches instructions from areas other than
on-chip peripheral module space*
Fetches instructions from on-chip peripheral
module space*
Fetches instructions from external memory
space in single-chip mode
Fetches instructions from access reserved
area.*
Accesses stack when the stack pointer value
is even address
Accesses stack when the stack pointer value
is odd
Accesses word data from even addresses
Accesses word data from odd addresses
Accesses external memory space in single-
chip mode
Accesses to reserved area*
Accesses word data from even addresses
Accesses word data from odd addresses
Accesses external memory space in single-
chip mode
Accesses to reserved area*
2
1
Rev. 3.00 Mar. 14, 2006 Page 79 of 804
2
2
1
Section 4 Exception Handling
Address Error
No (normal)
Occurs
No (normal)
Occurs
Occurs
Occurs
No (normal)
Occurs
No (normal)
No (normal)
Occurs
Occurs
No (normal)
No (normal)
Occurs
Occurs
REJ09B0104-0300
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