R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 73

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

2.6.2
Figure 2.13 shows the data formats in memory.
The H8SX CPU can access word data and longword data which are stored at any addresses in
memory. When word data begins at an odd address or longword data begins at an address other
than a multiple of 4, a bus cycle is divided into two or more accesses. For example, when
longword data begins at an odd address, the bus cycle is divided into byte, word, and byte
accesses. In this case, these accesses are assumed to be individual bus cycles.
However, instructions to be fetched, word and longword data to be accessed during execution of
the stack manipulation, branch table manipulation, block transfer instructions, and MAC
instruction should be located to even addresses.
When SP (ER7) is used as an address register to access the stack, the operand size should be word
size or longword size.
Memory Data Formats
Data Type
1-bit data
Byte data
Word data
Longword data
Figure 2.13 Memory Data Formats
Address 2M + 1
Address 2N + 1
Address 2N + 2
Address 2N + 3
Address
Address 2M
Address 2N
Address L
Address L
MSB
MSB
MSB
7
7
6
Data Format
Rev. 3.00 Mar. 14, 2006 Page 35 of 804
5
4
3
2
1
REJ09B0104-0300
LSB
LSB
LSB
0
0
Section 2 CPU