R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 705

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

18.5
18.5.1
1. The following points should be noted since the frequency of φ (Iφ: system clock and Pφ:
2. All the on-chip peripheral modules (except for the DMAC) operate on the Pφ. Therefore, note
3. The relationship between the system clock and peripheral module clock is Iφ ≥ Pφ. In addition,
4. Figure 18.5 shows the clock modification timing. After a value is written to SCKCR, this LSI
peripheral module clock) supplied to each module changes according to the setting of SCKCR.
Select a clock division ratio that is within the operation guaranteed range of clock cycle time
t
When the HCAN and SSU are in use, 8 MHz ≤ Iφ ≤ 40 MHz, and 8 MHz ≤ Pφ ≤ 20 MHz, the
following settings are not permitted: Iφ < 8MHz, Iφ > 40 MHz, Pφ < 8MHz, and Pφ > 20 MHz.
When the HCAN and SSU are not in use, 8 MHz ≤ Iφ ≤ 40 MHz, and 8 MHz ≤ Pφ ≤ 35 MHz,
the following settings are not permitted: Iφ < 8MHz, Iφ > 40 MHz, Pφ < 8MHz, and Pφ > 35
MHz.
that the time processing of modules such as a timer and SCI differs before and after changing
the clock division ratio.
In addition, wait time for clearing software standby mode differs by changing the clock
division ratio. For details, see section 19.7.3, Setting Oscillation Settling Time after Clearing
Software Standby Mode.
the system clock setting has priority. Accordingly, Pφ may have the frequency set by bits ICK2
to ICK0 regardless of the settings of bits PCK2 to PCK0.
waits for the current bus cycle to complete. After the current bus cycle completes, each clock
frequency will be modified within one cycle (worst case) of the external clock.
cyc
External
clock
I
Bus master
shown in the AC timing of electrical characteristics.
Usage Notes
Notes on Clock Pulse Generator
Operating clock
specified in SCKCR
CPU
Figure 18.5 Clock Modification Timing
after the bus cycle completion
One cycle (worst case)
CPU
Operating clock changed
Rev. 3.00 Mar. 14, 2006 Page 667 of 804
Section 18 Clock Pulse Generator
CPU
REJ09B0104-0300