R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 718

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 19 Power-Down Modes
The registers of the module for which module stop mode is selected cannot be read from or written
to.
19.5
19.5.1
When the SLEEP instruction is executed when the SSBY bit in SBYCR is 0, the CPU enters sleep
mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are
retained. Other peripheral functions do not stop.
19.5.2
Sleep mode is exited by any interrupt, signals on the RES pin, and a reset caused by a watchdog
timer overflow.
1. Clearing by interrupt
2. Clearing by RES pin
3. Clearing by reset caused by watchdog timer overflow
19.6
When the ACSE bit in MSTPCRA is set to 1 and all modules controlled by MSTPCR are stopped
(MSTPCRA, MSTPCRB = H'FFFFFFFF, MSTPCRC = H'FF00), executing a SLEEP instruction
with the SSBY bit in SBYCR cleared to 0 will cause all modules (except for the watchdog timer),
the bus controller, and the I/O ports to stop operating, and to make a transition to all-module-
clock-stop mode at the end of the bus cycle.
All-module-clock-stop mode is cleared by an external interrupt (NMI or IRQ0 to IRQ14 pins),
RES pin input, or an internal interrupt (watchdog timer), and the CPU returns to the normal
program execution state via the exception handling state. All-module-clock-stop mode is not
cleared if interrupts are disabled or interrupts other than NMI are masked on the CPU side.
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REJ09B0104-0300
When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep
mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the
CPU.
Setting the RES pin level low selects the reset state. After the stipulated reset input duration,
driving the RES pin high makes the CPU start the reset exception processing.
Sleep mode is exited by an internal reset caused by a watchdog timer overflow.
Sleep Mode
Transition to Sleep Mode
Clearing Sleep Mode
All-Module-Clock-Stop Mode