R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 175

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Channel 3
• DMA source address register_3 (DSAR_3)
• DMA destination address register_3 (DDAR_3)
• DMA offset register_3 (DOFR_3)
• DMA transfer count register_3 (DTCR_3)
• DMA block size register_3 (DBSR_3)
• DMA mode control register_3 (DMDR_3)
• DMA address control register_3 (DACR_3)
• DMA module request select register_3 (DMRSR_3)
7.2.1
DSAR is a 32-bit readable/writable register that specifies the transfer source address. DSAR
updates the transfer source address every time data is transferred. When DDAR is specified as the
destination address (the DIRS bit in DACR is 1) in single address mode, DSAR is ignored.
Although DSAR can always be read from by the CPU, it must be read from in longwords and
must not be written to while data for the channel is being transferred.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
DMA Source Address Register (DSAR)
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
Rev. 3.00 Mar. 14, 2006 Page 137 of 804
Section 7 DMA Controller (DMAC)
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
REJ09B0104-0300
R/W
R/W
R/W
R/W
24
16
0
0
8
0
0
0