R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 619

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Note:
Bit
0
*
Bit Name
SCO
This is a write-only bit. This bit is always read as 0.
Initial
Value
0
R/W
(R)/W*
Description
Source Program Copy Operation
Requests the on-chip programming/erasing program to
be downloaded to the on-chip RAM. When this bit is set
to 1, the on-chip program which is selected by FPCS or
FECS is automatically downloaded in the on-chip RAM
area specified by FTDAR.
In order to set this bit to 1, the RAM emulation mode
must be canceled, H'A5 must be written to FKEY, and
this operation must be executed in the on-chip RAM.
Dummy read of FCCS must be executed twice
immediately after setting this bit to 1. All interrupts must
be disabled during download. This bit is cleared to 0
when download is completed.
During program download initiated with this bit,
particular processing which accompanies bank-
switching of the program storage area is executed.
Before a download request, initialize the VBR contents
to H'00000000. After download is completed, the VBR
contents can be changed.
0: Download of the programming/erasing program is
[Clearing condition]
•
1: Download of the programming/erasing program is
[Setting conditions] (When all of the following conditions
are satisfied)
•
•
•
not requested.
When download is completed
requested.
Not in RAM emulation mode (the RAMS bit in
RAMER is cleared to 0)
H'A5 is written to FKEY
Setting of this bit is executed in the on-chip RAM
Section 17 Flash Memory (0.18-(m F-ZTAT Version)
Rev. 3.00 Mar. 14, 2006 Page 581 of 804
REJ09B0104-0300