R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 159

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 5.7
Table 5.8 shows an setting example of the priority control function over the DMAC and the
transfer request control state. Although the DMAC priority levels can be assigned for each
channel, table 5.8 gives a single channel description. Thus, transfer for each channel can be
performed independently by assigning the different priority levels.
Table 5.8
Interrupt
Control
Mode
0
2
Interrupt Control
Mode
0
2
Interrupt
Priority
Default
IPR setting
CPU Priority Control
Example of Priority Control Function Setting and Control State
CPUPCE in
CPUPCR
0
1
0
1
Interrupt
Mask Bit
I = any
I = 0
I = 1
I2 to I0
CPUP2 to
CPUP0
Any
B'000
B'100
B'100
B'100
B'000
Any
B'000
B'000
B'011
B'100
B'101
B'110
B'111
B'101
B'101
1
0
IPSETE in
CPUPCR
0
1
DMAP2 to
DMAP0
Any
B'000
B'000
B'011
B'101
B'101
Any
B'000
B'101
B'101
B'101
B'101
B'101
B'101
B'101
B'101
CPUP2 to CPUP0
B'111 to B'000
B'000
B'100
B'111 to B'000
I2 to I0
Rev. 3.00 Mar. 14, 2006 Page 121 of 804
Control Status
Enabled
Enabled
Masked
Masked
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Masked
Masked
Enabled
Enabled
Transfer Request Control State
DMAC
Section 5 Interrupt Controller
Updating of CPUP2
to CPUP0
Enabled
Disabled
Enabled
Disabled
REJ09B0104-0300